US5499385A
Expired / Lapsed
US
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Method for accessing and transmitting data to/from a memory in packets
Assignee: Rambus Inc
•
Filing: 1992-03-05
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Granted: 1996-03-12
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Expires: 2012-03-05
Abstract
Abstract A method of transmitting digital information to a memory circuit of a plurality of memory circuits of a computer system through a multiline bus of the computer system is described. The plurality of memory circuits are coupled together via the multiline bus. The multiline bus has a total number of lines less than a total number of bits in any single address. A first word of a packet is transmitted onto the multiline bus. A second word of the packet is then transmitted onto the multiline bus. The second word of the packet includes a first portion of an address. A third word of the packet is transmitted onto the multiline bus. The third word of the packet includes a second portion of the address.
Inventors
- 👤 Michael Farmwald
- 👤 Mark Horowitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:23
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1066; G06; G06F; G06F11/00; G06F11/006; G06F12/00; G06F12/02; G06F12/0215; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661; G06F12/0684; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F13/1668; G06F13/1678; G06F13/1689; G06F13/1694; G06F13/36; G06F13/368; G06F13/376; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4239; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/409; G11C11/4096; G11C29/00; G11C29/70; G11C29/88; G11C5/00; G11C5/02; G11C5/04; G11C5/06; G11C5/063; G11C5/066; G11C7/1006; G11C7/1012; G11C7/1015; G11C7/1045; G11C7/1057; G11C7/1069; G11C7/1072; G11C7/1078; G11C7/1084; G11C7/22; G11C7/222; G11C7/225; G11C8/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1048; G11C2207/00; G11C2207/10; G11C2207/105; G11C2207/108; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
238 words
A method of addressing a first memory among a plurality of memories coupled to a bi-directional multiline bus for a memory operation from a master also coupled to the bus, comprising the steps of: (A) transmitting from the master a first word of a packet to the bus, wherein the bus (1) does not include separate device selection lines for the memories and (2) has a total number of lines less than a total number of bits in any single address, wherein the first word includes (1) a device ID of the first memory and (2) a first portion of an address that alone cannot address any memory location within each of the memories; (B) receiving the first word in the first memory from the bus, wherein the first memory is enabled to receive subsequent words of the packet after receiving the device ID in the first word from the bus; (C) transmitting from the master a second word of the packet to the first memory via the bus, wherein the second word includes a second portion of the address such that the first memory is selected and addressed for the memory operation without a separate device selection line: (D) combining the first and second portions of the address together in the first memory to form the address for addressing a location within the first memory; (E) Reading/Writing the location within the first memory using the combined address.
Claim 2
Independent Claim
238 words
A method of addressing a first memory among a plurality of memories coupled to a bi-directional multiline bus for a memory operation from a master also coupled to the bus, comprising the steps of: (A) transmitting from the master a first word of a packet to the bus, wherein the bus (1) does not include separate device selection lines for the memories and (2) has a total number of lines less than a total number of bits in any single address, wherein the first word includes (1) a device ID of the first memory and (2) a first portion of an address that alone cannot address any memory location within each of the memories; (B) receiving the first word in the first memory from the bus, wherein the first memory is enabled to receive subsequent words of the packet after receiving the device ID in the first word from the bus; (C) transmitting from the master a second word of the packet to the first memory via the bus, wherein the second word includes a second portion of the address such that the first memory is selected and addressed for the memory operation without a separate device selection line: (D) combining the first and second portions of the address together in the first memory to form the address for addressing a location within the first memory; (E) Reading/Writing the location within the first memory using the combined address.
Claim 3
Dependent Claim
52 words
The method as claimed in claim 1, further comprising the step of transmitting to the bus a third word of the packet from the master prior to the step (A), wherein the third word includes (1) start information indicating start of the packet and (2) control information for controlling the memory operation.
Claim 4
Dependent Claim
22 words
The method as claimed in claim 2, wherein the third word further comprises packet origin information that indicates origin of the packet.
Claim 5
Dependent Claim
27 words
The method as claimed in claim 1, wherein the second word of the packet further comprises validity information that indicates whether the packet is a valid packet.
Claim 6
Dependent Claim
56 words
The method as claimed in claim 1, wherein the step (C) further comprises the step of transmitting from the master a plurality of words of the packet before transmitting the second word, wherein the plurality of words include a third portion of the address, wherein the address is formed by the first, second, and third portions.
Claim 7
Dependent Claim
19 words
The method as claimed in claim 1, wherein each of the memories is a dynamic random access memory (DRAM).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-12 | 1999-09-11 | 2000-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-12 | 2003-09-11 | 2004-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-12 | 2007-09-11 | 2008-03-12 | $7700.00 | Window Closed / Lapsed |