Programmable logic module and architecture for field programmable gate array device

Claim 2

A core architecture for a user-programmable gate array integrated circuit, including: an array of logic function modules, each of said modules having at least one input and at least one output; a general interconnect architecture imposed on said array, said general interconnect architecture comprising a plurality of horizontal and vertical general interconnect channels, each of said horizontal and vertical general interconnect channels including a plurality of interconnect conductors, individual ones of said general interconnect conductors connectable to each other and to the inputs and outputs of the logic function modules by user-programmable interconnect elements; and a local interconnect architecture imposed on said array, said local interconnect architecture comprising local interconnect channels, each local interconnect channel running between at least two adjacent ones of said logic function modules and including a plurality of local interconnect conductors, first ones of said local interconnect conductors hardwired to the outputs of said adjacent ones of said logic function modules, and second ones of said local interconnect conductors connectable to each other and to the inputs of the logic function modules by user-programmable interconnect elements.

Claim 3

The core architecture of claim 1, wherein said local interconnect channel runs between a pair of said adjacent ones of said logic function modules.

Claim 4

The core architecture of claim 1 wherein each of said logic function modules includes a plurality of function units selected from combinatorial units and sequential units.

Claim 5

The core architecture of claim 1 wherein said user-programmable interconnect elements are antifuses.

Claim 6

The core architecture of claim 3, wherein a first logic function module connected to an individual local interconnect channel comprises a leftmost combinatorial unit, a center sequential unit, and a rightmost combinatorial unit, and wherein a second logic function module connected to said individual local interconnect channel comprises a leftmost combinatorial unit, a center sequential unit, and a rightmost combinatorial unit.

Claim 7

The core architecture of claim 3, wherein a first logic function module connected to an individual local interconnect channel comprises a leftmost combinatorial unit, a center sequential unit, and a rightmost combinatorial unit, and wherein a second logic function module connected to said individual local interconnect channel comprises a leftmost sequential unit, a center sequential unit, and a rightmost combinatorial unit.

Claim 8

The core architecture of claim 3, wherein a first logic function module connected to an individual local interconnect channel comprises a leftmost combinatorial unit, a center sequential unit, and a rightmost sequential unit, and wherein a second logic function module connected to said individual local interconnect channel comprises a leftmost combinatorial unit, a center sequential unit, and a rightmost combinatorial unit.

Claim 9

A combinatorial logic unit comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output; a first logic gate having a first input connected to a fifth data input conductor, a second input connected to a sixth data input conductor and an output connected to the control inputs of said first and second multiplexers; a second logic gate having a first input connected to a seventh data input conductor, a second input connected to an eighth data input conductor and an output connected to the control input of said third multiplexer; an output buffer having an input connected to said output of said third multiplexer and an output connected to an output conductor; a plurality of interconnect conductors intersecting said data and control input conductors of said first, second, and third multiplexers, said plurality of interconnect conductors selectively connectable to individual ones of said data and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said interconnect conductors and an output connected to a second one of said interconnect conductors.

Claim 10

A combinatorial logic unit comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output; a first logic gate having a first input connected to a fifth data input conductor, a second input connected to a sixth data input conductor and an output connected to the control inputs of said first and second multiplexers; a second logic gate having a first input connected to a seventh data input conductor, a second input connected to an eighth data input conductor and an output connected to the control input of said third multiplexer; an output buffer having an input connected to said output of said third multiplexer and an output connected to an output conductor; a plurality of interconnect conductors intersecting said data and control input conductors of said first, second, and third multiplexers, said plurality of interconnect conductors selectively connectable to individual ones of said data and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said interconnect conductors and an output connected to a second one of said interconnect conductors.

Claim 11

The combinatorial logic unit of claim 8 wherein said first logic gate is an AND gate and said second logic gate is an OR gate.

Claim 12

The combinatorial logic unit of claim 8 wherein said user-programmable interconnect elements are antifuses.

Claim 13

A sequential logic unit comprising: a data flip-flop having a data input, a clock input, and an output; a first data multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input connected to a first control input conductor, and an output; a second data multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to said output of said first multiplexer, a control input, and an output connected to the data input of said data flip-flop; a clock multiplexer having a first data input connected to a global clock conductor, a second data input connected to the complement of the signal on said global clock conductor, a third data input connected to a clock input conductor, a fourth data input connected to the complement of the signal on said clock input conductor, a first control input connected to a clock select control input conductor, a second control input connected to a clock polarity control input conductor, and an output connected to said clock input of said data flip-flop; an output buffer having an input connected to said output of said data flip-flop output, and an output connected to an output conductor; and a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, and third multiplexers, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements.

Claim 14

A sequential logic unit comprising: a data flip-flop having a data input, a clock input, and an output; a first data multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input connected to a first control input conductor, and an output; a second data multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to said output of said first multiplexer, a control input, and an output connected to the data input of said data flip-flop; a clock multiplexer having a first data input connected to a global clock conductor, a second data input connected to the complement of the signal on said global clock conductor, a third data input connected to a clock input conductor, a fourth data input connected to the complement of the signal on said clock input conductor, a first control input connected to a clock select control input conductor, a second control input connected to a clock polarity control input conductor, and an output connected to said clock input of said data flip-flop; an output buffer having an input connected to said output of said data flip-flop output, and an output connected to an output conductor; and a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, and third multiplexers, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements.

Claim 15

The sequential logic unit of claim 11 further including: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements; and a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 16

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output; a first logic gate having a first input connected to a fifth data input conductor, a second input connected to a sixth data input conductor and an output connected to the control inputs of said first and second multiplexers; a second logic gate having a first input connected to a seventh data input conductor, a second input connected to an eighth data input conductor and an output connected to the control input of said third multiplexer; a first output buffer having an input connected to said output of said third multiplexer and an output connected to a first output conductor; a data flip-flop having a data input, a clock input, and an output; a fourth data multiplexer having a first data input connected to the output of said first output buffer, a second data input connected to a ninth data input conductor, a control input connected to a first control input conductor, and an output; a fifth data multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a second control input conductor, and an output connected to the data input of said data flip-flop; a clock multiplexer having a first data input connected to a global clock conductor, a second data input connected to the complement of the signal on said global clock conductor, a third data input connected to a clock input conductor, a fourth data input connected to the complement of the signal on said clock input conductor, a first control input connected to a clock select control input conductor, a second control input connected to a clock polarity control input conductor, and an output connected to said clock input of said data flip-flop; a second output buffer having an input connected to said output of said data flip-flop output, and an output connected to a second output conductor; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third fourth fifth and said clock multiplexers and said first and second output conductors of said first and second output buffers, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said interconnect conductors and an output connected to a second one of said interconnect conductors.

Claim 17

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output; a first logic gate having a first input connected to a fifth data input conductor, a second input connected to a sixth data input conductor and an output connected to the control inputs of said first and second multiplexers; a second logic gate having a first input connected to a seventh data input conductor, a second input connected to an eighth data input conductor and an output connected to the control input of said third multiplexer; a first output buffer having an input connected to said output of said third multiplexer and an output connected to a first output conductor; a data flip-flop having a data input, a clock input, and an output; a fourth data multiplexer having a first data input connected to the output of said first output buffer, a second data input connected to a ninth data input conductor, a control input connected to a first control input conductor, and an output; a fifth data multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a second control input conductor, and an output connected to the data input of said data flip-flop; a clock multiplexer having a first data input connected to a global clock conductor, a second data input connected to the complement of the signal on said global clock conductor, a third data input connected to a clock input conductor, a fourth data input connected to the complement of the signal on said clock input conductor, a first control input connected to a clock select control input conductor, a second control input connected to a clock polarity control input conductor, and an output connected to said clock input of said data flip-flop; a second output buffer having an input connected to said output of said data flip-flop output, and an output connected to a second output conductor; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third fourth fifth and said clock multiplexers and said first and second output conductors of said first and second output buffers, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said interconnect conductors and an output connected to a second one of said interconnect conductors.

Claim 18

The programmable logic module of claim 13 wherein said data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements; and a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 19

The programmable logic module of claim 13 wherein said first logic gate is an AND gate and said second logic gate is an OR gate.

Claim 20

The programmable logic module of claim 13 wherein said user-programmable interconnect elements are antifuses.

Claim 21

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output; a first logic gate having a first input connected to a fifth data input conductor, a second input connected to a sixth data input conductor and an output connected to the control inputs of said first and second multiplexers; a second logic gate having a first input connected to a seventh data input conductor, a second input connected to an eighth data input conductor and an output connected to the control input of said third multiplexer; a first output buffer having an input connected to said output of said third multiplexer and an output; a data flip-flop having a data input, a clock input, and an output; a fourth data multiplexer having a first data input connected to the output of said first output buffer, a second data input connected to a ninth data input conductor, a control input connected to a first control input conductor, and an output; a fifth data multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a second control input conductor, and an output connected to the data input of said data flip-flop; a clock multiplexer having a first data input connected to a global clock conductor, a second data input connected to the complement of the signal on said global clock conductor, a third data input connected to a clock input conductor, a fourth data input connected to the complement of the signal on said clock input conductor, a first control input connected to a clock select control input conductor, a second control input connected to a clock polarity control input conductor, and an output connected to said clock input of said data flip-flop; a second output buffer having an input connected to said output of said data flip-flop output, and an output connected to an output conductor; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third fourth fifth and said clock multiplexers, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to the output of said first output buffer, a second one of said local interconnect conductors connected to the output of said second output buffer, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third fourth fifth and said clock multiplexers, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said interconnect conductors and an output connected to a second one of said interconnect conductors.

Claim 22

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output; a first logic gate having a first input connected to a fifth data input conductor, a second input connected to a sixth data input conductor and an output connected to the control inputs of said first and second multiplexers; a second logic gate having a first input connected to a seventh data input conductor, a second input connected to an eighth data input conductor and an output connected to the control input of said third multiplexer; a first output buffer having an input connected to said output of said third multiplexer and an output; a data flip-flop having a data input, a clock input, and an output; a fourth data multiplexer having a first data input connected to the output of said first output buffer, a second data input connected to a ninth data input conductor, a control input connected to a first control input conductor, and an output; a fifth data multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a second control input conductor, and an output connected to the data input of said data flip-flop; a clock multiplexer having a first data input connected to a global clock conductor, a second data input connected to the complement of the signal on said global clock conductor, a third data input connected to a clock input conductor, a fourth data input connected to the complement of the signal on said clock input conductor, a first control input connected to a clock select control input conductor, a second control input connected to a clock polarity control input conductor, and an output connected to said clock input of said data flip-flop; a second output buffer having an input connected to said output of said data flip-flop output, and an output connected to an output conductor; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third fourth fifth and said clock multiplexers, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to the output of said first output buffer, a second one of said local interconnect conductors connected to the output of said second output buffer, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third fourth fifth and said clock multiplexers, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said interconnect conductors and an output connected to a second one of said interconnect conductors.

Claim 23

The programmable logic module of claim 17 wherein said data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements; and a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 24

The programmable logic module of claim 17 wherein said first logic gate is an AND gate and said second logic gate is an OR gate.

Claim 25

The programmable logic module of claim 17 wherein said user-programmable interconnect elements are antifuses.

Claim 26

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output; a first logic gate having a first input connected to a fifth data input conductor, a second input connected to a sixth data input conductor and an output connected to the control inputs of said first and second multiplexers; a second logic gate having a first input connected to a seventh data input conductor, a second input connected to an eighth data input conductor and an output connected to the control input of said third multiplexer; a first output buffer having an input connected to said output of said third multiplexer and an output; a first data flip-flop having a data input, a clock input, and an output; a fourth data multiplexer having a first data input connected to the output of said first output buffer, a second data input connected to a ninth data input conductor, a control input connected to a first control input conductor, and an output; a fifth data multiplexer having a first data input connected the output of said first data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a second control input conductor, and an output connected to the data input of said first data flip-flop; a first clock multiplexer having a first data input connected to a global clock conductor, a second data input connected to the complement of the signal on said global clock conductor, a third data input connected to a clock input conductor, a fourth data input connected to the complement of the signal on said clock input conductor, a first control input connected to a clock select control input conductor, a second control input connected to a clock polarity control input conductor, and an output connected to said clock input of said data flip-flop; a second output buffer having an input connected to said output of said first data flip-flop, and an output connected to an output conductor; a second data flip-flop having a data input, a clock input, and an output; a sixth data multiplexer having a first data input connected to a tenth data input conductor, a second data input connected to an eleventh data input conductor, a control input connected to a fourth control input conductor, and an output; a seventh data multiplexer having a first data input connected the output of said second data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a fifth control input conductor, and an output connected to the data input of said second data flip-flop; a second clock multiplexer having a first data input connected to a global clock conductor, a second data input connected to the complement of the signal on said global clock conductor, a third data input connected to a clock input conductor, a fourth data input connected to the complement of the signal on said clock input conductor, a first control input connected to a clock select control input conductor, a second control input connected to a clock polarity control input conductor, and an output connected to said clock input of said data flip-flop; a third output buffer having an input connected to said output of said second data flip-flop, and an output connected to an output conductor; a plurality of general interconnect conductors, at least some of said general interconnect conductors forming first intersections with at least some of said first through eleventh data input conductors, said first through sixth control input conductors said first and second clock multiplexers, and said first and second clock control input and clock control polarity input conductors; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to the output of said first output buffer, a second one of said local interconnect conductors connected to the output of said second output buffer, at least some of said local interconnect conductors forming second intersections with at least some of said first through eleventh data input conductors, said first through sixth control input conductors said first and second clock multiplexers, and said first and second clock control input and clock control polarity input conductors; an inverter having an input connected to a first one of said interconnect conductors and an output connected to a second one of said interconnect conductors; and a plurality of user-programmable interconnect elements disposed at selected ones of said first and second intersections.

Claim 27

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output; a first logic gate having a first input connected to a fifth data input conductor, a second input connected to a sixth data input conductor and an output connected to the control inputs of said first and second multiplexers; a second logic gate having a first input connected to a seventh data input conductor, a second input connected to an eighth data input conductor and an output connected to the control input of said third multiplexer; a first output buffer having an input connected to said output of said third multiplexer and an output; a first data flip-flop having a data input, a clock input, and an output; a fourth data multiplexer having a first data input connected to the output of said first output buffer, a second data input connected to a ninth data input conductor, a control input connected to a first control input conductor, and an output; a fifth data multiplexer having a first data input connected the output of said first data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a second control input conductor, and an output connected to the data input of said first data flip-flop; a first clock multiplexer having a first data input connected to a global clock conductor, a second data input connected to the complement of the signal on said global clock conductor, a third data input connected to a clock input conductor, a fourth data input connected to the complement of the signal on said clock input conductor, a first control input connected to a clock select control input conductor, a second control input connected to a clock polarity control input conductor, and an output connected to said clock input of said data flip-flop; a second output buffer having an input connected to said output of said first data flip-flop, and an output connected to an output conductor; a second data flip-flop having a data input, a clock input, and an output; a sixth data multiplexer having a first data input connected to a tenth data input conductor, a second data input connected to an eleventh data input conductor, a control input connected to a fourth control input conductor, and an output; a seventh data multiplexer having a first data input connected the output of said second data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a fifth control input conductor, and an output connected to the data input of said second data flip-flop; a second clock multiplexer having a first data input connected to a global clock conductor, a second data input connected to the complement of the signal on said global clock conductor, a third data input connected to a clock input conductor, a fourth data input connected to the complement of the signal on said clock input conductor, a first control input connected to a clock select control input conductor, a second control input connected to a clock polarity control input conductor, and an output connected to said clock input of said data flip-flop; a third output buffer having an input connected to said output of said second data flip-flop, and an output connected to an output conductor; a plurality of general interconnect conductors, at least some of said general interconnect conductors forming first intersections with at least some of said first through eleventh data input conductors, said first through sixth control input conductors said first and second clock multiplexers, and said first and second clock control input and clock control polarity input conductors; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to the output of said first output buffer, a second one of said local interconnect conductors connected to the output of said second output buffer, at least some of said local interconnect conductors forming second intersections with at least some of said first through eleventh data input conductors, said first through sixth control input conductors said first and second clock multiplexers, and said first and second clock control input and clock control polarity input conductors; an inverter having an input connected to a first one of said interconnect conductors and an output connected to a second one of said interconnect conductors; and a plurality of user-programmable interconnect elements disposed at selected ones of said first and second intersections.

Claim 28

The programmable logic module of claim 21 wherein at least one of said first and second data flip-flops further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements; and a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said general interconnect conductors and connectable to least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 29

The programmable logic module of claim 21 wherein said first logic gate is an AND gate and said second logic gate is an OR gate.

Claim 30

The programmable logic module of claim 21 wherein said user programmable interconnect elements are antifuses.