Programmable logic device with multiplexer-based programmable interconnections

Claim 2

In a programmable logic array having a plurality of programmable logic elements, each of which has at least one programmable logic element input lead and at least one programmable logic element output lead, means for selectively connecting said programmable logic element output leads to said programmable logic element input leads comprising: a plurality of conductors extending between said programmable logic elements; means for connecting said programmable logic element output leads to said conductors; a multiplexer having a plurality of multiplexer input leads and a multiplexer output lead for selectively connecting any one of its multiplexer input leads to its multiplexer output lead, each of said multiplexer input leads being connected with a fixed connection to a respective one of said conductors, said conductors being substantially parallel to one another adjacent to said fixed connections, said fixed connections allowing said conductors to be spaced closer to one another than would be possible using a programmable interconnection between each of said multiplexer input leads and a respective one of said conductors; and means for selectively connecting said multiplexer output lead to any of a plurality of said programmable logic element input leads, wherein said conductors cross a plurality of said programmable logic element input leads without possibility of interconnection with those programmable logic element input leads, and wherein said means for selectively connecting comprises: a multiplexer output leads which crosses said plurality of programmable logic element input leads; and means for selectively connecting said multiplexer output lead to at least one of said plurality of programmable logic element input leads.

Claim 3

In a programmable logic array having a plurality of programmable logic elements, each of which has at least one programmable logic element input lead and at least one programmable logic element output lead, means for selectively connecting said programmable logic element output leads to said programmable logic element input leads comprising: a plurality of conductors extending between said programmable logic elements; means for connecting said programmable logic element output leads to said conductors; a multiplexer having a plurality of multiplexer input leads and a multiplexer output lead for selectively connecting any one of its multiplexer input leads to its multiplexer output lead, each of said multiplexer input leads being connected with a fixed connection to a respective one of said conductors, said conductors being substantially parallel to one another adjacent to said fixed connections, said fixed connections allowing said conductors to be spaced closer to one another than would be possible using a programmable interconnection between each of said multiplexer input leads and a respective one of said conductors; and means for selectively connecting said multiplexer output lead to any of a plurality of said programmable logic element input leads, wherein said means for selectively connecting said multiplexer output lead to each of at least some of said plurality of programmable logic element input leads comprises a programmable interconnection between said multiplexer output lead and at least one of said plurality of programmable logic element input leads.

Claim 4

In a programmable logic array having a plurality of programmable logic elements, each of which has at least one programmable logic element input lead and at least one programmable logic element output lead, means for selectively connecting said programmable logic element output leads to said programmable logic element input leads comprising: a plurality of conductors extending between said programmable logic elements; means for connecting said programmable logic element output leads to said conductors; a multiplexer having a plurality of multiplexer input leads and a multiplexer output lead for selectively connecting any one of its multiplexer input leads to its multiplexer output lead, each of said multiplexer input leads being connected with a fixed connection to a respective one of said conductors, said conductors being substantially parallel to one another adjacent to said fixed connections, said fixed connections allowing said conductors to be spaced closer to one another than would be possible using a programmable interconnection between each of said multiplexer input leads and a respective one of said conductors; and means for selectively connecting said multiplexer output lead to any of a plurality of said programmable logic element input leads, wherein said means for selectively connecting said multiplexer output lead to each of at least some of said plurality of programmable logic element input leads comprises a programmable interconnection between said multiplexer output lead and at least one of said plurality of programmable logic element input leads.

Claim 5

A programmable logic array integrated circuit comprising: a plurality of logic modules, each of which has a plurality of inputs and at least one output for producing as said output a programmable logical function of said inputs, said logic modules being grouped in a plurality of logic array blocks, said blocks being disposed on said circuit in a two dimensional array including intersecting rows and columns of said blocks; a plurality of first conductors adjacent to each of said logic array blocks, the first conductors adjacent to each block being adjacent to the logic modules within said block for selectively applying the outputs of the logic modules in each block to the inputs of any of the logic modules in that block; a plurality of second conductors extending substantially parallel to a first dimension of said array, said second conductors being grouped in a plurality of groups, each of which is adjacent to a respective one of said rows of blocks, each second conductor in each of said groups of second conductors extending continuously past substantially all of the blocks in the adjacent row; means for selectively applying the outputs of the logic modules in a row to the second conductors in the group adjacent to said row; means for selectively applying the signals on the second conductors in each group to the inputs of the logic modules in the row adjacent to said group; a plurality of third conductors extending substantially parallel to a second dimension of said array, said third conductors being grouped in a plurality of groups, each of which is adjacent to a respective one of said columns of blocks, each third conductor in each of said groups of third conductors extending continuously past substantially all of the blocks in the adjacent column; means for selectively applying the outputs of the logic modules in each column to the third conductors in the group adjacent to said column; and means for selectively connecting said third conductors to said second conductors, wherein each of said logic modules comprises: flip-flop means for registering said output of said logic module; and means for selectively bypassing said flip-flop means so that said output of said logic module is also available unregistered.

Claim 6

A programmable logic array integrated circuit comprising: a plurality of logic modules, each of which has a plurality of inputs and at least one output for producing as said output a programmable logical function of said inputs, said logic modules being grouped in a plurality of logic array blocks, said blocks being disposed on said circuit in a two dimensional array including intersecting rows and columns of said blocks; a plurality of first conductors adjacent to each of said logic array blocks, the first conductors adjacent to each block being adjacent to the logic modules within said block for selectively applying the outputs of the logic modules in each block to the inputs of any of the logic modules in that block; a plurality of second conductors extending substantially parallel to a first dimension of said array, said second conductors being grouped in a plurality of groups, each of which is adjacent to a respective one of said rows of blocks, each second conductor in each of said groups of second conductors extending continuously past substantially all of the blocks in the adjacent row; means for selectively applying the outputs of the logic modules in a row to the second conductors in the group adjacent to said row; means for selectively applying the signals on the second conductors in each group to the inputs of the logic modules in the row adjacent to said group; a plurality of third conductors extending substantially parallel to a second dimension of said array, said third conductors being grouped in a plurality of groups, each of which is adjacent to a respective one of said columns of blocks, each third conductor in each of said groups of third conductors extending continuously past substantially all of the blocks in the adjacent column; means for selectively applying the outputs of the logic modules in each column to the third conductors in the group adjacent to said column; and means for selectively connecting said third conductors to said second conductors, wherein each of said logic modules comprises: flip-flop means for registering said output of said logic module; and means for selectively bypassing said flip-flop means so that said output of said logic module is also available unregistered.

Claim 7

The circuit defined in claim 3 wherein each of said logic modules comprises: look up table means having a plurality of programmable stored values, each of which is a possible value of said output that can be provided in response to a respective one of the possible combinations of said inputs to said logic module; and means responsive to said inputs to said logic module for producing as said outputs from said logic module the stored value that corresponds to the respective combination of said inputs currently being applied to said logic module.

Claim 8

The circuit defined in claim 3 wherein said means for selectively bypassing said flip-flop means comprises: a switch having two input terminals and an output terminal, a first of said input terminals being connected to an input of said flip-flop means, and a second of said input terminals being connected to an output of said flip-flop means; and programmable means for causing said switch to connect a selected one of its input terminals to its output terminal.

Claim 9

The circuit defined in claim 3 wherein said means for selectively applying the outputs of the logic modules in a row to the second conductors in the group adjacent to said row comprises: tri-state driver means connected between the output of each logic module in said row and a respective one of the second conductors in the group adjacent to said row.

Claim 10

The circuit defined in claim 3 further comprising: means for applying the output of each of the logic modules in a block to a respective one of the first conductors adjacent to that block; a programmable logic connector connected between a plurality of said first conductors adjacent to each block and each input of the logic modules in that block; and programmable function control element means for controlling each programmable logic connector to select at least one of the first conductors connected to that programmable logic connector as a source for a signal applied to the logic module input connected to that programmable logic connector.

Claim 11

The circuit defined in claim 3 wherein said means for selectively applying the signals on the second conductors in each group to the inputs of the logic modules in the row adjacent to said group comprises: a programmable logic connector connected between a plurality of the second conductors in said group and each input of the logic modules in said row; and programmable function control element means for controlling each programmable logic connector to select at least one of the second conductors connected to that programmable logic connector as a source for a signal applied to the logic module input connected to that programmable logic connector.

Claim 12

The circuit defined in claim 8 wherein each programmable logic connector is connected between less than all of said second conductors in said group and the logic module in said row adjacent to said group.

Claim 13

The circuit defined in claim 3 wherein said means for selectively applying the outputs of the logic modules in a column to the third conductors in the group adjacent to said column comprises: tri-state driver means connected between the output of each logic module in said column and a respective one of the third conductors in the group adjacent to said column.

Claim 14

The circuit defined in claim 3 wherein said means for selectively connecting said third conductors to said second conductors comprises: a switch connected between (1) the output of each logic module and a third conductor in the group of third conductors adjacent to the column of blocks including that logic module, and (2) a second conductor in the group of second conductors adjacent to the row of blocks including that logic module; and programmable function control element means for controlling each switch to select either the logic module output or the third conductor connected to that switch as the source of the signal applied to the second conductor connected to that switch.

Claim 15

A programmable logic array integrated circuit comprising: a plurality of regions of programmable logic disposed on said circuit in a two-dimensional array, each of said regions of programmable logic having a plurality of data input terminals and at least one data output terminal, and each of said regions of programmable logic being programmable to perform any of a plurality of logic functions on input signals applied to the data input terminals in order to produce an output signal which is applied to the data output terminal; a first plurality of signal conductors, each of which extends along a first of the two dimensions of said two-dimensional array, and each of which extends continuously without interruption past a first multiplicity of said regions of programmable logic which are spaced from one another in a direction along said first dimension; a second plurality of signal conductors, each of which extends along a second of the two dimensions of said two-dimensional array, and each of which extends continuously without interruption past a second multiplicity of said regions of programmable logic which are spaced from one another in a direction along said second dimension; and a plurality of programmable switches each being connected to one of said first conductors for allowing said first conductors to be connected to at least one of a plurality of said second conductors to which each of said programmable switches is connected, each programmable switch being adjacent to a respective one of said regions of programmable logic and being usable to connect the first conductor to which that programmable switch is connected to a second conductor without preventing the adjacent region of programmable logic from being programmed to perform any of said plurality of logic functions, wherein each of said programmable switches comprises: a first branch conductor permanently connected to the first conductor; a plurality of second branch conductors each permanently connected to one of the second conductors; and a programmable link for allowing said first branch conductor to be connected to one of said second branch conductors, wherein the programmable link of each of said programmable switches is disposed on said circuit at a location distinct and separate from the permanent connections of said first and second branch conductors to the first and second conductors.

Claim 16

A programmable logic array integrated circuit comprising: a plurality of regions of programmable logic disposed on said circuit in a two-dimensional array, each of said regions of programmable logic having a plurality of data input terminals and at least one data output terminal, and each of said regions of programmable logic being programmable to perform any of a plurality of logic functions on input signals applied to the data input terminals in order to produce an output signal which is applied to the data output terminal; a first plurality of signal conductors, each of which extends along a first of the two dimensions of said two-dimensional array, and each of which extends continuously without interruption past a first multiplicity of said regions of programmable logic which are spaced from one another in a direction along said first dimension; a second plurality of signal conductors, each of which extends along a second of the two dimensions of said two-dimensional array, and each of which extends continuously without interruption past a second multiplicity of said regions of programmable logic which are spaced from one another in a direction along said second dimension; and a plurality of programmable switches each being connected to one of said first conductors for allowing said first conductors to be connected to at least one of a plurality of said second conductors to which each of said programmable switches is connected, each programmable switch being adjacent to a respective one of said regions of programmable logic and being usable to connect the first conductor to which that programmable switch is connected to a second conductor without preventing the adjacent region of programmable logic from being programmed to perform any of said plurality of logic functions, wherein each of said programmable switches comprises: a first branch conductor permanently connected to the first conductor; a plurality of second branch conductors each permanently connected to one of the second conductors; and a programmable link for allowing said first branch conductor to be connected to one of said second branch conductors, wherein the programmable link of each of said programmable switches is disposed on said circuit at a location distinct and separate from the permanent connections of said first and second branch conductors to the first and second conductors.

Claim 17

The apparatus defined in claim 12 wherein said two-dimensional array is bounded by a first pair of edges which are substantially perpendicular to said first dimension and by a second pair of edges which are substantially perpendicular to said second dimension, and wherein each of said first conductors extends continuously substantially the entire distance between said first pair of edges.

Claim 18

The apparatus defined claim 13 wherein each of said second conductors extends continuously substantially the entire distance between said second pair of edges.

Claim 19

The apparatus defined in claim 12 wherein said regions of programmable logic are arranged in a plurality of rows which are spaced from one another along said second dimension, and wherein said first conductors are disposed on said circuit in the spaces between adjacent rows.

Claim 20

The apparatus defined in claim 15 wherein some of said first conductors are disposed in the space between each adjacent pair of rows.

Claim 21

The apparatus defined in claim 15 wherein said regions of programmable logic are also arranged in a plurality of columns which are substantially perpendicular to said rows, said columns being spaced from one another along said first dimension, and wherein said second conductors are disposed on said circuit in the spaces between adjacent columns.

Claim 22

The apparatus defined in claim 17 wherein some of said second conductors are disposed in the space between each adjacent pair of columns.

Claim 23

The apparatus defined in claim 12 wherein the programmable link of each of said programmable switches is a programmable transistor switch.

Claim 24

The apparatus defined in claim 12 wherein said means for connecting the data input and output terminals of each of said regions of programmable logic to selected ones of said conductors comprises: means for allowing the data output terminal of each of said regions of programmable logic to be connected to an adjacent one of said first conductors and an adjacent one of said second conductors.

Claim 25

The apparatus defined in claim 12 wherein the programmable switch adjacent to each region of programmable logic can connect either an adjacent second conductor or the data output terminal of the adjacent region of programmable logic to an adjacent first conductor.

Claim 26

The apparatus defined in claim 12 wherein said means for connecting the data input and output terminals of each of said regions of programmable logic to selected ones of said conductors comprises: a tri-state driver in the connection between each of said data output terminals and the selected conductor.

Claim 27

The apparatus defined in claim 12 wherein each connection established by said means for connecting is established through a tri-state driver.