Complementary bipolar polysilicon emitter devices

Claim 1

An integrated circuit structure including complementary PNP and NPN bipolar transistors of similar profile and approximately matched performance and at least one field effect (MOS) transistor adjacent the bipolar transistors on a common substrate produced by the steps of: defining at least one buried layer within said substrate; for each bipolar transistor, forming a bipolar transistor intrinsic base region as a buried layer within said substrate having a doping concentration different from that of the substrate; depositing only a single layer of polysilicon on said substrate; for each bipolar transistor, forming an insulating isolation ring within said polysilicon layer around a region where a bipolar transistor emitter is to be formed, the ring having an inside region and an outside region of polysilicon; for each bipolar transistor, selectively forming a self-aligned bipolar transistor emitter within said substrate below the inside regions of polysilicon; for each bipolar transistor, selectively forming an extrinsic base within said substrate below the outside region of polysilicon; wherein the emitters and extrinsic bases of the NPN and PNP transistors are formed in two drive-in steps; wherein an N-type emitter of the NPN transistor is formed simultaneously with an N-type extrinsic base of the PNP transistor; and wherein a P-type emitter of the PNP transistor is formed simultaneously with a P-type extrinsic base of the NPN transistor; for each MOS transistor, forming a MOS transistor gate within the single layer of polysilicon; for each MOS transistor, forming MOS transistor source and drain regions within the substrate; and providing surface contacts to the bipolar transistor emitters and base contacting regions and to the NOS transistor gate, source and drain regions.