Salicide compatible CMOS process with a differential oxide implant mask

Claim 1

In a method of manufacturing a CMOS device wherein the method includes the sequential steps of providing a semiconductor substrate of p-type conductivity; implanting n-type impurity into selected regions of the semiconductor substrate to define n-type substrate regions and p-type substrate regions; forming field oxide regions in the semiconductor substrate to electrically isolate the n-type and p-type substrate regions to thereby define n-type active device substrate regions and p-type active device substrate regions; forming a layer of gate dielectric material on the substrate surface in both the n-type and the p-type active device substrate regions; forming gate electrodes on the gate dielectric material in both the n-type and the p-type active device substrate regions; forming initial spacer dielectric material directly adjacent to exposed edges of the gate electrodes to define initial insulating sidewall spacers on said exposed edges; performing a low-energy, high-dosage implant of n-type impurity into the p-type active device substrate regions to define n-type source and drain regions of n-channel MOS transistors; performing a low energy, medium-dosage implant of n-type impurity into said n-type source and drain regions; forming a thermal differential oxide on the surface of the n-type and p-type active device substrate region such that said differential oxide grows at a first rate on the surface of said p-type active device substrate regions and at a second rate on the surface of said n-type active device substrate regions, the second rate being slower than the first rate; performing a medium-energy, high-dosage implant of p-type impurity into the n-type active device substrate regions to define p-type source and drain regions of p-channel MOS transistors; the additional steps of: performing an etchback of said differential oxide to remove said differential oxide, said etchback resulting in the removal of initial sidewall spacer material from said initial insulating sidewall spacers; forming additional sidewall spacer material to replace removed initial sidewall spacer material, thereby defining final reconstituted insulating sidewall spacers on the edges of the gate electrodes; and forming a salicide in said n-type and p-type source and drain regions by depositing a metal and exposing said substrate to temperature treatment.