EP0164449A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Process for producing a semiconductor integrated circuit device including a MISFET
Assignee: Hitachi Ltd
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Filing: 1984-12-24
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Granted: —
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Expires: 2004-12-24
Abstract
Abstract In a process for fabricating a semiconductor integrated circuit device which is provided with N-channel and P-channel MISFETs each having a pair of side wall spacers (6) formed simultaneously at both sides of the gate electrodes (5), the P-channel MISFET has its source and drain regions (15), formed by a boron ion implantation using the gate electrode (5) and the paired side wall spacers (6) as a mask. The boron having a high diffusion velocity is suppressed from diffusing below the gate electrode (5).
Inventors
- 👤 Kousuke Hitachi-Nishikiso 205 Okuyama
- 👤 Norio Hitachi-Maehara-Ryo Suzuki
- 👤 Satoshi Meguro
- 👤 Kouichi Nagasawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 06:00
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/60; H10D64/00; H10D64/01; H10D64/021; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0184; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
124 words
A process for fabricating a semiconductor integrated circuit device including a MISFET, wherein (a) a gate insulating film (4) is formed on the main surface of a semiconductor substrate (1), (b) a gate electrode (5) is formed on said gate insulating film (4), and (c) source and drain regions (8, 15, 18) are formed in said substrate (1) by impurity introduction using said gate electrode (5) as a mask, characterised in that, prior to step (c), a pair of side wall spacers (6) is formed on both sides of said gate electrode (5), and that said impurity for forming said sburce and drain regions (7, 15, 18) is introduced in using said gate electrode (5) and said side wall spacers (6) as a mask.
Claim 2
Dependent Claim
124 words
A process for fabricating a semiconductor integrated circuit device including a MISFET, wherein (a) a gate insulating film (4) is formed on the main surface of a semiconductor substrate (1), (b) a gate electrode (5) is formed on said gate insulating film (4), and (c) source and drain regions (8, 15, 18) are formed in said substrate (1) by impurity introduction using said gate electrode (5) as a mask, characterised in that, prior to step (c), a pair of side wall spacers (6) is formed on both sides of said gate electrode (5), and that said impurity for forming said sburce and drain regions (7, 15, 18) is introduced in using said gate electrode (5) and said side wall spacers (6) as a mask.
Claim 3
Dependent Claim
90 words
The process of claim 1 for fabricating a semiconductor integrated circuit device including N-channel and P-channel MISFETs, wherein a pair of side wall spacers (6) is formed at.both sides of the gate electrode (5) of each MISFET and wherein the source and drain regions (7; 18) of said N-channel MISFET are formed by an N-type impurity introduction and the source and drain regions (15) of said P-channel MISFET are formed by a P-type impurity introduction, using said gate electrode (5) and said paired side wall spacers (6) as a mask.
Claim 4
Dependent Claim
61 words
The process of claim 2, wherein said source and/or drain regions of said N-channel MISFET are composed of a first semiconductor region (7) having a high impurity concentration, and a second semiconductor region (8) formed between said first semiconductor region (7) and a region below said gate electrode (5) and having a lower impurity concentration than the first semiconductor region (7).
Claim 5
Dependent Claim
58 words
The process of claim 3, wherein said first and second semiconductor regions (7, 8) of said N-channel MISFET are formed by an N-type impurity introduction using said gate electrode (5) and said paired side wall spacers (6) as a mask, and wherein said second semiconductor region (8) has a larger diffusion depth than said first semiconductor region (7).
Claim 6
Dependent Claim
94 words
The process of claim 3, wherein said second semiconductor region (8) of said N-channel MISFET is formed by an N-type impurity introduction using said gate electrode (5) as a mask, thereafter said paired side wall spacers (6) are formed at both sides of said gate electrode (5) and then said first semiconductor region (7X is formed by an N-type impurity introduction using said gate electrode (5) and said paired side wall spacers (6) as a mask, and wherein said first semiconductor region (7) has a larger diffusion depth than said second semiconductor region (8).
Claim 7
Dependent Claim
20 words
The process of any of claims 3 to 5, wherein the impurity for forming said semiconductor region (8) is phosphor.
Claim 8
Dependent Claim
22 words
The process of any of claims 3 to 6, wherein the impurity for forming said first semiconductor region (7) is mainly arsenic.
Claim 9
Dependent Claim
28 words
The process of any of claims 2 to 7, wherein the side wall spacers (6) of said P-channel MISFET are formed simultaneously with those of said N-channel MISFET.
References Cited (Backward Citations)
No citation records indexed.
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