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US4358890A Expired / Lapsed US ⏱️ 0.0 years remaining

Process for making a dual implanted drain extension for bucket brigade device tetrode structure

Assignee: International Business Machines Corp
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Filing: 1981-08-18
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Granted: 1982-11-16
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Expires: 2001-08-18
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Abstract

Abstract The invention is the structure and process for making a bucket brigade device which comprises the merger of an MOS capacitor with an MOSFET device to form the charge transfer cell. A first thin N-type region is implanted at a first concentration in a portion of the P-type channel region of an FET device adjacent to the drain diffusion. A second region is implanted with N-type dopant at a second concentration less than the first concentration, adjacent to and continuous with the first implanted region. The N-type concentration in the second region is just sufficient to compensate for the P-type background doping in the channel region. This structure increases the charge transfer efficiency for the cell and reduces its sensitivity of the threshold voltage to the source-drain voltage. The gate for the device has a substantial overlap over the drain and a minimal overlap over the source and the gate to drain capacitance per unit area is maximized by maintaining a uniformly thin oxide layer across the gate region.

Inventors

  • 👤 Lawrence G. Heller
  • 👤 Harry J. Jones
  • 👤 Harish N. Kotecha
  • 👤 Donald A. Soderman

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 23:44
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/891; H10D84/895; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307; H10D84/01; H10D84/0198; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/811; H10D84/813

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 451 words
A process for making a serially connected plurality of bucket brigade devices in a silicon semiconductor substrate of P-type conductivity and a dopant concentration of from 7 to 10×10 15 /cm 3 , each of said devices occupying a device area bounded on opposed ends by a first and a second diffusion of N-type conductivity, the first diffusion of a first device serving as the second diffusion of a next serially connected device, with a thick insulating layer overlying said semiconductor substrate having a plurality of windows therethrough, each said window juxtaposed over and exposing a corresponding one of said device areas, comprising the steps of: growing a thin insulating layer of silicon dioxide on the surface of said substrate in each of said device areas, to a thickness of from 500 A to 700 A; depositing a first ion implantation blocking mask over a first portion of each of said device areas, masking a channel region adjacent to said first diffusion and exposing a capacitor plate region adjacent to said second diffusion, said first mask having an edge defining the boundary between said channel region and said capacitor plate region; ion implanting N-type conductivity dopant ions at an energy of 65 Kev and a first dose of from 1 to 5×10 13 /cm 2 through said thin insulating layer and into said substrate in said capacitor plate region of each of said device areas, forming an N-type conductivity capacitor plate in said substrate which has a terminal edge at said boundary between said channel region and said plate region and which electrically contacts said second diffusion; removing said first ion implantation blocking mask and depositing a second ion implantation blocking mask over a second portion of each of said device areas, masking a first, high threshold voltage portion of said channel region adjacent to said first diffusion and exposing a second, low threshold voltage portion of said channel region adjacent to said terminal edge of said capacitor plate; ion implanting said N-type conductivity ions at a second dose of from 0.5 to 1×10 12 /cm 2 , which is lower than said first dose, through said thin insulating layer and into said substrate in said low threshold voltage portion of said channel region, forming an N-type conductivity doped low threshold voltage region having a threshold voltage of between 0 and -1 volts; said high threshold voltage portion of said channel region having a threshold voltage of approximately +1 volts; removing said second mask and depositing a gate electrode on said thin insulator layer over said channel region and said capacitor plate region in each of said device areas; whereby an improved, serially connected plurality of bucket brigade devices is formed.
Claim 2
Dependent Claim 451 words
A process for making a serially connected plurality of bucket brigade devices in a silicon semiconductor substrate of P-type conductivity and a dopant concentration of from 7 to 10×10 15 /cm 3 , each of said devices occupying a device area bounded on opposed ends by a first and a second diffusion of N-type conductivity, the first diffusion of a first device serving as the second diffusion of a next serially connected device, with a thick insulating layer overlying said semiconductor substrate having a plurality of windows therethrough, each said window juxtaposed over and exposing a corresponding one of said device areas, comprising the steps of: growing a thin insulating layer of silicon dioxide on the surface of said substrate in each of said device areas, to a thickness of from 500 A to 700 A; depositing a first ion implantation blocking mask over a first portion of each of said device areas, masking a channel region adjacent to said first diffusion and exposing a capacitor plate region adjacent to said second diffusion, said first mask having an edge defining the boundary between said channel region and said capacitor plate region; ion implanting N-type conductivity dopant ions at an energy of 65 Kev and a first dose of from 1 to 5×10 13 /cm 2 through said thin insulating layer and into said substrate in said capacitor plate region of each of said device areas, forming an N-type conductivity capacitor plate in said substrate which has a terminal edge at said boundary between said channel region and said plate region and which electrically contacts said second diffusion; removing said first ion implantation blocking mask and depositing a second ion implantation blocking mask over a second portion of each of said device areas, masking a first, high threshold voltage portion of said channel region adjacent to said first diffusion and exposing a second, low threshold voltage portion of said channel region adjacent to said terminal edge of said capacitor plate; ion implanting said N-type conductivity ions at a second dose of from 0.5 to 1×10 12 /cm 2 , which is lower than said first dose, through said thin insulating layer and into said substrate in said low threshold voltage portion of said channel region, forming an N-type conductivity doped low threshold voltage region having a threshold voltage of between 0 and -1 volts; said high threshold voltage portion of said channel region having a threshold voltage of approximately +1 volts; removing said second mask and depositing a gate electrode on said thin insulator layer over said channel region and said capacitor plate region in each of said device areas; whereby an improved, serially connected plurality of bucket brigade devices is formed.

References Cited (Backward Citations)

US3789267A Cited
US3767983A Cited
US4100513A Cited
US4087832A Cited
US4142199A Cited
US4771229A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1985-11-15 1986-05-17 1986-11-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1989-11-15 1990-05-17 1990-11-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1993-11-15 1994-05-17 1994-11-16 $7700.00 Window Closed / Lapsed

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