Removable sidewall spaces for lightly doped drain formation using one mask level

Claim 2

A process for forming lightly doped drains (LDD) (28,36) on devices (10,12) in MOS integrated circuits comprising the steps of: forming gates (18,20) for MOS devices (10,12) on an integrated circuit substrate (14,16); forming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; forming a disposable barrier material (26) over selected gates (18,20); implanting heavily doped source/drain regions (30,38) along the sidewall spacer (24) edges of the gates not covered by the disposable barrier (26) material while the remaining gates (18,20) are protected by the disposable barrier material (26); removing the disposable sidewall spacers (24) from along the edges of the gates (18,20) having the heavily doped source/drain regions (30,38); selectively implanting LDD regions (28,36) along the edges of the gates (18,20) having the heavily doped source/drain regions (30,38); removing the disposable barrier material (26) from over the selected gates (18,20); and driving in the source/drain regions (28,30,36,38) along the gate (18,20) edges in a thermal drive-in cycle.

Claim 3

The process of claim 1 in which only one mask level is employed in the formation of the LDDs(28,36).

Claim 4

The process of claim 1 in which source/drain regions (30,38) and LDDs (28,36) are subsequently formed along the other gate (18,20) edges previously protected by the disposable barrier material (26).

Claim 5

The process of claim 3 in which a dielectric is grown in a selectively thick pattern (32,34) to protect the LDDs (28,36) and source/drain regions (30,38) formed in the drive-in step.

Claim 6

The process of claim 3 in which permanent spacers (40) are formed along the gate (18,20) edges after the drive-in step.

Claim 7

The process of claim 1 in which a high energy p⁻ implant is employed to form p⁻ pocket regions (44).

Claim 8

A process for forming lightly doped drains (LDDs) (28,36) on both NMOS (10) and PMOS (12) devices together on a CMOS integrated circuit comprising the steps of: forming gates (18,20) for NMOS (10) and PMOS (12) devices in an integrated circuit substrate (14, 16); forming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; protecting gates (18,20) of a first conductivity type by covering them with a disposable barrier material (26); implanting heavily doped source/drain regions (30,38) along sidewall spacer (24) edges of gates of a second conductivity type, while gates (18,20) of the first conductivity type are protected by the disposable barrier material (26); removing the disposable sidewall spacer (24) from along the edges of the gates (18,20) of the second conductivity type; implanting LDDs (28,36) along the gate (18,20) edges of the second conductivity type while the gates (18,20) of the first conductivity type are protected by a disposable barrier material (26); removing the disposable barrier material (26) and driving in the source/drain regions (28,30,36,38) along the gate (18,20) edges of the first conductivity type in a thermal drive-in cycle.

Claim 9

A process for forming lightly doped drains (LDDs) (28,36) on both NMOS (10) and PMOS (12) devices together on a CMOS integrated circuit comprising the steps of: forming gates (18,20) for NMOS (10) and PMOS (12) devices in an integrated circuit substrate (14, 16); forming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; protecting gates (18,20) of a first conductivity type by covering them with a disposable barrier material (26); implanting heavily doped source/drain regions (30,38) along sidewall spacer (24) edges of gates of a second conductivity type, while gates (18,20) of the first conductivity type are protected by the disposable barrier material (26); removing the disposable sidewall spacer (24) from along the edges of the gates (18,20) of the second conductivity type; implanting LDDs (28,36) along the gate (18,20) edges of the second conductivity type while the gates (18,20) of the first conductivity type are protected by a disposable barrier material (26); removing the disposable barrier material (26) and driving in the source/drain regions (28,30,36,38) along the gate (18,20) edges of the first conductivity type in a thermal drive-in cycle.

Claim 10

A process for forming lightly doped drains (LDDs) (28,36) on both NMOS (10) and PMOS(12) devices together on a CMOS integrated circuit using one mask level comprising forming gates (18,20) for NMOS (10) and PMOS (12) devices on p areas (16) and on areas (14) respectively; forming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; depositing a resist mask (26) over gates (18,20) of a first conductivity type; implanting heavily doped source/drain regions (30,38) along the edges of the sidewall spacers (24) of gates (18,20) of a second conductivity type; removing the disposable sidewall spacers (24) from along the gate (18,20) edges of the second conductivity type; implanting LDDs (28,36) along the gate (18,20) edges of the second conductivity type; stripping the resist mask (26) from the gates (18,20) of the first conductivity type; removing the remaining disposable sidewall spacers (24); driving in the source/drain regions (30,38) and LDDs (28,36) along the gate (18,20) edges of the second conductivity type in a first thermal drive-in cycle in an oxidizing ambient to grow silicon dioxide(32,34) over the surface of the substrate (14,16) wherein the oxide (32) over the source/drain regions (30,38) and LDDs (28,36) by the gates (18,20) of the second conductivity type is thicker than the oxide (34) over future source/drain regions (30,38) by the gates of the first conductivity type; reforming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; implanting heavily doped source/drain regions (30,38) along the edges of the sidewall spacers (24) of gates (18,20) of the first conductivity type; removing all disposable sidewall spacers (24) from along the gate (18,20) edges; implanting LDDs (28,36) along the gate (18,20) edges of the first conductivity type; and driving in the source/drain regions (30,38) and LDDs (28,36) along the gate (18,20) edges of the first conductivity type in a second thermal drive-in cycle.

Claim 11

A process for forming lightly doped drains (LDDs) (28,36) on both NMOS (10) and PMOS(12) devices together on a CMOS integrated circuit using one mask level comprising forming gates (18,20) for NMOS (10) and PMOS (12) devices on p areas (16) and on areas (14) respectively; forming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; depositing a resist mask (26) over gates (18,20) of a first conductivity type; implanting heavily doped source/drain regions (30,38) along the edges of the sidewall spacers (24) of gates (18,20) of a second conductivity type; removing the disposable sidewall spacers (24) from along the gate (18,20) edges of the second conductivity type; implanting LDDs (28,36) along the gate (18,20) edges of the second conductivity type; stripping the resist mask (26) from the gates (18,20) of the first conductivity type; removing the remaining disposable sidewall spacers (24); driving in the source/drain regions (30,38) and LDDs (28,36) along the gate (18,20) edges of the second conductivity type in a first thermal drive-in cycle in an oxidizing ambient to grow silicon dioxide(32,34) over the surface of the substrate (14,16) wherein the oxide (32) over the source/drain regions (30,38) and LDDs (28,36) by the gates (18,20) of the second conductivity type is thicker than the oxide (34) over future source/drain regions (30,38) by the gates of the first conductivity type; reforming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; implanting heavily doped source/drain regions (30,38) along the edges of the sidewall spacers (24) of gates (18,20) of the first conductivity type; removing all disposable sidewall spacers (24) from along the gate (18,20) edges; implanting LDDs (28,36) along the gate (18,20) edges of the first conductivity type; and driving in the source/drain regions (30,38) and LDDs (28,36) along the gate (18,20) edges of the first conductivity type in a second thermal drive-in cycle.

Claim 12

A process for forming lightly doped drains (LDDs) (28,36) on both NMOS (10) and PMOS(12) devices together on a CMOS integrated circuit using one mask level comprising forming gates (18,20) for NMOS (10) and PMOS (12) devices on p areas (16) and n areas (14) respectively; forming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; depositing a resist mask (26) over gates (20) of a first conductivity type; implanting heavily doped source/drain regions (30) along the edges of the sidewall spacers (24) of gates (18) of a second conductivity type; removing the disposable sidewall spacers (24) from along the gate (18) edges of the second conductivity type; implanting LDDs (28) along the gate (18) edges of the second conductivity type; stripping the resist mask (26) from the gates (20) of the first conductivity type; removing substantially all of the remaining disposable sidewall spacers (24); driving in the source/drain regions (30) and LDDs (28) along the gate (18) edges of the second conductivity type in a first thermal drive-in cycle in an oxidizing ambient to grow silicon dioxide (32,34) over the surface of the substrate (14,16) wherein the oxide (32) over the source/drain regions (30) and LDDs (28) by the gates of the second conductivity type is thicker than the oxide (34) over the future source/drain regions (38) by the gates (20) of the first conductivity type; implanting LDDs (36) along the gate (20) edges of the first conductivity type; forming permanent spacers (40) along the gate edges; implanting heavily doped source/drain regions (38) along the permanent spacer (40) edges of the first conductivity type; and driving in the source/drain regions (38) and LDDs (36) along the gate (20) edges of the first conductivity type in a second thermal drive-in cycle.

Claim 13

A process for forming lightly doped drains (LDDs) (28,36) on both NMOS (10) and PMOS(12) devices together on a CMOS integrated circuit using one mask level comprising forming gates (18,20) for NMOS (10) and PMOS (12) devices on p areas (16) and n areas (14) respectively; forming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; depositing a resist mask (26) over gates (20) of a first conductivity type; implanting heavily doped source/drain regions (30) along the edges of the sidewall spacers (24) of gates (18) of a second conductivity type; removing the disposable sidewall spacers (24) from along the gate (18) edges of the second conductivity type; implanting LDDs (28) along the gate (18) edges of the second conductivity type; stripping the resist mask (26) from the gates (20) of the first conductivity type; removing substantially all of the remaining disposable sidewall spacers (24); driving in the source/drain regions (30) and LDDs (28) along the gate (18) edges of the second conductivity type in a first thermal drive-in cycle in an oxidizing ambient to grow silicon dioxide (32,34) over the surface of the substrate (14,16) wherein the oxide (32) over the source/drain regions (30) and LDDs (28) by the gates of the second conductivity type is thicker than the oxide (34) over the future source/drain regions (38) by the gates (20) of the first conductivity type; implanting LDDs (36) along the gate (20) edges of the first conductivity type; forming permanent spacers (40) along the gate edges; implanting heavily doped source/drain regions (38) along the permanent spacer (40) edges of the first conductivity type; and driving in the source/drain regions (38) and LDDs (36) along the gate (20) edges of the first conductivity type in a second thermal drive-in cycle.

Claim 14

A MOS integrated circuit having devices (10,12) with lightly doped drains (LDDs) (28,36) made by the process comprising the steps of : forming gates (18,20) for MOS devices (10,12) on an integrated circuit substrate (14,16); forming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; forming a disposable barrier material (26) over selected gates (18,20); implanting heavily doped source/drain regions (30,38) along the sidewall spacer (32) edges of the gates not covered by the disposable barrier material (26) while the remaining gates (18,20) are protected by the disposable barrier material (26); removing the disposable sidewall spacers (24) from along the edges of the gates (18,20) having the heavily doped source/drain regions (30,38); selectively implanting LDD regions (28,36) along the edges of the gates (18,20) having the heavily doped source/drain regions (30,38); removing the disposable barrier material (26) from over the selected gates (18,20); and driving in the source/drain regions (28,30,36,38) along the gate (18,20) edges in a thermal drive-in cycle.

Claim 15

A MOS integrated circuit having devices (10,12) with lightly doped drains (LDDs) (28,36) made by the process comprising the steps of : forming gates (18,20) for MOS devices (10,12) on an integrated circuit substrate (14,16); forming disposable, cleanly removable sidewall spacers (24) along the gate (18,20) edges; forming a disposable barrier material (26) over selected gates (18,20); implanting heavily doped source/drain regions (30,38) along the sidewall spacer (32) edges of the gates not covered by the disposable barrier material (26) while the remaining gates (18,20) are protected by the disposable barrier material (26); removing the disposable sidewall spacers (24) from along the edges of the gates (18,20) having the heavily doped source/drain regions (30,38); selectively implanting LDD regions (28,36) along the edges of the gates (18,20) having the heavily doped source/drain regions (30,38); removing the disposable barrier material (26) from over the selected gates (18,20); and driving in the source/drain regions (28,30,36,38) along the gate (18,20) edges in a thermal drive-in cycle.