Method of making CMOS device and contacts therein by enhanced oxidation of selectively implanted regions

Claim 2

In a process for forming complementary metal-oxide-semiconductor substrate devices in a wafer having regions defined therein for n-channel and p-channel devices which contain insulated gate structures, the sequence comprising: selectively implanting the wafer with n-type dopant, excluding one or more selected regions which includes the p-channel device region; heating the wafer in an oxidizing atmosphere for driving-in the n-type dopant to form the n-channel device source and drain and other n-doped regions, while also forming a first oxide masking layer on the implanted-implanted surfaces; and using the first oxide masking layer as a mask, doping the wafer with a p-type dopant to form the p-channel device source and drain and other p-doped regions.

Claim 3

In a process for forming complementary metal-oxide-semiconductor substrate devices in a wafer having regions defined therein for n-channel and p-channel devices which contain insulated gate structures, the sequence comprising: selectively implanting the wafer with n-type dopant, excluding one or more selected regions which includes the p-channel device region; heating the wafer in an oxidizing atmosphere for driving-in the n-type dopant to form the n-channel device source and drain and other n-doped regions, while also forming a first oxide masking layer on the implanted-implanted surfaces; using the first oxide masking layer as a mask, doping the wafer with a p-type impurity to form the p-channel device source and drain and other p-doped regions; removing the first oxide masking layer; forming on the wafer an interlayer dielectric layer having openings to selected contact regions including openings to the n-type and p-type substrate contact regions associated with the n-channel and p-channel devices; forming a silicon layer on the wafer; selectively doping the silicon layer with n-type dopant, excluding one or more selected regions which includes the p-channel device region; heating the wafer in an oxidizing atmosphere for diffusing the n-type dopant to increase the dopant concentration at the silicon-to-n-type substrate contact regions and to simultaneously and selectively form a second oxide masking layer at the n-doped surfaces of the silicon layer; and using the second oxide masking layer as a mask, doping the wafer with a p-type dopant to increase the p-type dopant concentration at the p-type contact region.

Claim 4

In a process for forming complementary metal-oxide-semiconductor substrate devices in a wafer having regions defined therein for n-channel and p-channel devices which contain insulated gate structures, the sequence comprising: selectively implanting the wafer with n-type dopant, excluding one or more selected regions which includes the p-channel device region; heating the wafer in an oxidizing atmosphere for driving-in the n-type dopant to form the n-channel device source and drain and other n-doped regions, while also forming a first oxide masking layer on the implanted-implanted surfaces; using the first oxide masking layer as a mask, doping the wafer with a p-type impurity to form the p-channel device source and drain and other p-doped regions; removing the first oxide masking layer; forming on the wafer an interlayer dielectric layer having openings to selected contact regions including openings to the n-type and p-type substrate contact regions associated with the n-channel and p-channel devices; forming a silicon layer on the wafer; selectively doping the silicon layer with n-type dopant, excluding one or more selected regions which includes the p-channel device region; heating the wafer in an oxidizing atmosphere for diffusing the n-type dopant to increase the dopant concentration at the silicon-to-n-type substrate contact regions and to simultaneously and selectively form a second oxide masking layer at the n-doped surfaces of the silicon layer; and using the second oxide masking layer as a mask, doping the wafer with a p-type dopant to increase the p-type dopant concentration at the p-type contact region.

Claim 5

The process of claim 1 or 2 further comprising: removing the second oxide masking layer; depositing a layer of metal on the wafer; selectively patterning the resulting dual layer of metal-silicon to form interconnections; and forming a dielectric isolation layer over the wafer.

Claim 6

The process of claim 3 wherein the gates are silicon, the n-type dopant is arsenic, and the p-type dopant is boron.

Claim 7

The process of claim 3 wherein subsequent to the second step of doping the wafer with a p-type impurity dopant, the wafer is heated to establish the n-type and the p-type dopant concentrations at the respective silicon-to-substrate contact regions.

Claim 8

The process of forming improved contacts in a CMOS structure having insulated gate NMOS and PMOS devices and n-type and p-type contact regions formed in a semiconductor substrate, comprising: forming a layer of silicon over the structure; selectively doping regions of the silicon with one of the n-type dopants arsenic or phosphorus, the selected doped regions including silicon regions contacting n-type substrate contact regions; heating the structure in an oxidizing atmosphere for diffusing the n-type dopant to thereby increase the dopant concentration at the contact between the silicon-to-n-type substrate contact regions and for simultaneously and selectively forming an oxide masking layer at the n-type doped surface regions of the silicon layer; using the oxide layer as a mask, doping the silicon with p-type dopant; and heating the structure to diffuse the n-type and p-type dopants to thereby increase the dopant concentration at the respective silicon-to-n-type substrate and silicon-to-p-type substrate contacts.

Claim 9

The process of forming improved contacts in a CMOS structure having insulated gate NMOS and PMOS devices and n-type and p-type contact regions formed in a semiconductor substrate, comprising: forming a layer of silicon over the structure; selectively doping regions of the silicon with one of the n-type dopants arsenic or phosphorus, the selected doped regions including silicon regions contacting n-type substrate contact regions; heating the structure in an oxidizing atmosphere for diffusing the n-type dopant to thereby increase the dopant concentration at the contact between the silicon-to-n-type substrate contact regions and for simultaneously and selectively forming an oxide masking layer at the n-type doped surface regions of the silicon layer; using the oxide layer as a mask, doping the silicon with p-type dopant; and heating the structure to diffuse the n-type and p-type dopants to thereby increase the dopant concentration at the respective silicon-to-n-type substrate and silicon-to-p-type substrate contacts.

Claim 10

The process of claim 6 wherein the n-type dopant is arsenic.

Claim 11

The process of claim 6 or 8 wherein the p-type dopant is boron.