Spacer formation in a bicmos device

Claim 1

A method of constructing a first level contact structure on a BICMOS device having a PMOS transistor region and an NMOS transistor region on a substrate, the method comprising the steps of: a) masking and implanting a polysilicon layer with an n type dopant; b) masking and implanting said polysilicon layer with a p type dopant; c) depositing a nitride layer on the substrate; d) etching the polysilicon layer for forming a plurality of openings, an n-type gate on each of said PMOS transistor region and said NMOS transistor region and a p-type contact disposed on said substrate between said NMOS transistor region and said PMOS transistor region; e) forming a thermal oxide layer in said openings, said thermal oxide layer thicker on said n type polysilicon than on said p type polysilicon; f) etching said oxide so that said oxide on sidewalls of said p type polysilicon is substantially removed while leaving an effective amount of oxide on sidewalls of said gates to form spacers for isolation of said sidewalls of said n type polysilicon; and g) forming a silicide layer on said device, said silicide layer extending continuously from a first of said spacers on an active region of said NMOS transistor region, along sidewalls and an upper surface of said contact and to a second of said spacers on an active region of said PMOS transistor region.

Claim 2

A method of constructing a first level contact structure on a BICMOS device having a PMOS transistor region and an NMOS transistor region on a substrate, the method comprising the steps of: a) masking and implanting a polysilicon layer with an n type dopant; b) masking and implanting said polysilicon layer with a p type dopant; c) depositing a nitride layer on the substrate; d) etching the polysilicon layer for forming a plurality of openings, an n-type gate on each of said PMOS transistor region and said NMOS transistor region and a p-type contact disposed on said substrate between said NMOS transistor region and said PMOS transistor region; e) forming a thermal oxide layer in said openings, said thermal oxide layer thicker on said n type polysilicon than on said p type polysilicon; f) etching said oxide so that said oxide on sidewalls of said p type polysilicon is substantially removed while leaving an effective amount of oxide on sidewalls of said gates to form spacers for isolation of said sidewalls of said n type polysilicon; and g) forming a silicide layer on said device, said silicide layer extending continuously from a first of said spacers on an active region of said NMOS transistor region, along sidewalls and an upper surface of said contact and to a second of said spacers on an active region of said PMOS transistor region.