Method of fabricating a high performance bipolar and MOS device

Claim 1

A method of fabricating a bipolar device integrated with an MOS device, comprising the steps of: providing a semiconductor substrate having at least a first and a second isolated region; forming a gate dielectric layer over the first isolated region; forming an intrinsic base region in the second isolated region; depositing a polysilicon layer on the surface of the substrate; doping a predetermined region of the polysilicon layer which defines a polysilicon emitter region and a polysilicon gate region; removing portions of the polysilicon layer adjacent to the polysilicon emitter region and adjacent to the polysilicon gate region; forming a source and a drain region in the substrate adjacent to the polysilicon gate region; growing a silicon dioxide layer on the surface of the polysilicon layer and the semiconductor substrate surfacer, wherein a thicker amount of silicon dioxide grows over the polysilicon emitter region and the polysilicon gate region; etching the silicon dioxide layer so that only a portion of the silicon dioxide which is adjacent to the polysilicon gate region and the polysilicon emitter region remains, thereby creating silicon dioxide sidewall spacers; and forming a silicide layer on the polysilicon layer, the polysilicon emitter region, and the semiconductor substrate surface, wherein the silicide forms self-aligned contacts to the intrinsic base regions, the polysilicon emitter region, the source and drain regions, and the polysilicon gate region.

Claim 2

A method of fabricating a bipolar device integrated with an MOS device, comprising the steps of: providing a semiconductor substrate having at least a first and a second isolated region; forming a gate dielectric layer over the first isolated region; forming an intrinsic base region in the second isolated region; depositing a polysilicon layer on the surface of the substrate; doping a predetermined region of the polysilicon layer which defines a polysilicon emitter region and a polysilicon gate region; removing portions of the polysilicon layer adjacent to the polysilicon emitter region and adjacent to the polysilicon gate region; forming a source and a drain region in the substrate adjacent to the polysilicon gate region; growing a silicon dioxide layer on the surface of the polysilicon layer and the semiconductor substrate surfacer, wherein a thicker amount of silicon dioxide grows over the polysilicon emitter region and the polysilicon gate region; etching the silicon dioxide layer so that only a portion of the silicon dioxide which is adjacent to the polysilicon gate region and the polysilicon emitter region remains, thereby creating silicon dioxide sidewall spacers; and forming a silicide layer on the polysilicon layer, the polysilicon emitter region, and the semiconductor substrate surface, wherein the silicide forms self-aligned contacts to the intrinsic base regions, the polysilicon emitter region, the source and drain regions, and the polysilicon gate region.