Self-aligned silicide base contact for bipolar transistor

Claim 2

A semiconductor structure characterizea by: a semiconductor body having an overlying region of first conductivity type adjoining an upper surface; an electrically conductive region disposed on the upper surface and having side wall surfaces; a layer of insulating material formed on all the side wall surfaces; a layer of metal silicide disposed on the upper surface of the semiconductor boay, the metal silicide being separated from the electrically conductive region by the insulating material on the side wall surfaces; and a second region of opposite conductivity type adjoining the upper surface and beneath the electrically conductive region but nowhere in contact with the metal silicide.

Claim 3

.2. The structure of claim 1 characterized in that the semiconductor body further comprises an underlying region of the opposite conauctivity type.

Claim 4

The structure of claim 2 characterized in that the overlying region forms a base of a bipolar transistor, the secona region forms an emitter of the transistor, and the underlying region forms a collector of the transistor.

Claim 5

The structure of claim 1, 2 or 3 characterized in that the electrically conductive region forms an emitter contact of the transistor, and wherein the metal silicide forms a base contact of tne transistor.

Claim 6

Tne structure of claim 2, 3 or 4 characterized in that the overlying region comprises positively doped semiconductor material, and wherein the second region and the underlying region comprise negatively doped semiconductor materials.

Claim 7

The structure of any previous claim characterized in that the electrically conauctive region comprises impurity doped polycrystalline silicon.

Claim 8

The structure of any previous claim characterized in that the insulating material comprises silicon dioxide.

Claim 9

The structure of any previous claim characterized in that the metal silicide comprises a compound composed of silicon and a metal chosen from a group consisting of: titanium, vanadium, chromium, zirconium, niobium, molybdenum, hafnium, tantalum, tungsten, nickel, palladium, and platinum.

Claim 10

A process for forming a semiconductor structure, saia process being characterized by the steps of: providing a semiconductor substrate naving. a first conductivity region with a first upper surface tnereof; forming a second conductivity region disposed above ana contacting said first conductivity region, said second conductivity region having side walls extending upward from said first upper surface to a second upper surface of said second conductivity region; forming a layer of an oxide compound upon said upper surfaces and said side walls; removing portions of saia oxide compound from said upper surfaces until only a residual amount of oxide compound remains on said siae walls; and forming a conductive layer upon said first upper surface, said conductive layer being separated from said second conductivity region by the thickness of said residual amount of oxide compound.

Claim 11

A process for forming a semiconductor structure, saia process being characterized by the steps of: providing a semiconductor substrate naving. a first conductivity region with a first upper surface tnereof; forming a second conductivity region disposed above ana contacting said first conductivity region, said second conductivity region having side walls extending upward from said first upper surface to a second upper surface of said second conductivity region; forming a layer of an oxide compound upon said upper surfaces and said side walls; removing portions of saia oxide compound from said upper surfaces until only a residual amount of oxide compound remains on said siae walls; and forming a conductive layer upon said first upper surface, said conductive layer being separated from said second conductivity region by the thickness of said residual amount of oxide compound.

Claim 12

The process of claim 9 characterized in that said step of forming a layer of an oxide compound comprises growing said oxide compound from said first and second conductivity regions.

Claim 13

The process of claim 10 characterized in that said step of forming a layer of an oxide compound further comprises depositing oxide compound.

Claim 14

The process of claim 9, 10 or 11 characterized in that said step of removing portions of said oxide compound comprises a process or anisotropic etching.

Claim 15

The process of claim 12 characterized in that said process of anisotropic etching comprises reactive ion etching.

Claim 16

The process of any one of claims 9-13 characterized in that said conductive layer is an electrically conductive compound formea by the combination of a metal and the semiconductor material of said substrate.

Claim 17

The process of claim 14 characterized in that said step of forming a conductive layer comprises the steps of: depositing a layer of said metal upon said first upper surface; heating said layer of metal to an elevatea temperature for a period of time sufficient for said electrically conductive compound to form; and removing excess metal not forming said electrically conductive compound.

Claim 18

The process of claim 15 characterized in that said step of forming a conductive layer additionally comprises a step of implanting semiconductor material into said layer of metal prior to said step of heating said layer of metal.

Claim 19

The process of claim 14 or 15 characterized in that the metal is chosen from a group consisting of: titanium, vanadium, chromium, zirconium, niobium, molybdenum, hafnium, tantalum, tungsten, nickel, palladium, and platinum.

Claim 20

The process of any one of claims 9-17 characterized in that the material of said semiconductor substrate is silicon, and wherein said electrically conductive compound is silicide.

Claim 21

The process of any one of claims 9-18 characterized in that said first conductivity region forms a base of a bipolar transistor, wherein said second conductivity region forms an emitter of said transistor, and wherein said conductive layer forms a base contact of said transistor.

Claim 22

The process of any one of claims 9-19 characterized by the steps of: forming a thin insulative layer on top of said first upper surface prior to said step of forming a second conductivity region; and heating said substrate to an elevated temperature after said step of forming a second conductivity region to aiffuse a portion of said second conductivity region across said thin insulative layer, wherein said second conductivity region forms a tunnel emitter of a bipolar transistor, wherein said first conductivity region forms a base of said transistor, and wherein said conductive layer forms a base contact of said transistor.

Claim 23

The process of claim 9 characterized in that: said silicon substrate is lightly dopea; the step of forming said second region comprises forming a heavily doped buriea layer of a second conductivity type on a portion of said substrate; growing a lightly doped epitaxial layer of said second conductivity type on top of said buried layer; forming a field oxide layer extending into the said epitaxial layer to divide said epitaxial layer into first and second regions; implanting said first region with impurities of a first type to form a ligntly dopea base region of said first conductivity type; depositing a layer of polycrystalline silicon upon the upper surface of said substrate; implanting said polycrystalline silicon with impurities of a second type to form a heavily doped layer of said second conductivity type; selectively removing portions of said polycrystalline silicon leaving an emitter region positioned above and contacting said base region, and leaving a collector tap region above and contacting said second region, said emitter and collector tap regions having side walls extending upward from said base and second regions, respectively; said oxide forming step comprises forming a first oxide layer on top of saia substrate; said removing step comprises removing most of said first oxide layer by anisotropically etching said first oxide layer until the upper surfaces of said collector tap, base, and emitter regions are free of oxide, leaving a residual amount of oxide on said side walls; and said conductive layer forming step comprises depositing a layer of a first metal upon the upper surface of said base region; heating said layer of a first metal to an elevated temperature for a perioa of time sufficient for a silicide to form between said first metal and the silicon exposed on the upper surface of said base region, wherein said silicide forms a base contact that is separated from said emitter region by said residual amount of oxide; and removing excess first metal not forming said silicide.

Claim 24

The process of claim 21 characterized by the steps of: depositing a second oxide layer over the upper surface of said substrate after said step of removing excess first metal; selectively removing portions of said second oxiae layer to open contact holes to said tap region, said base contact, and said emitter region; depositing a layer of a second metal on top of said substrate; and selectively removing portions of said secona metal to form separate electrical connections with said collector tap region, said base contact, and said emitter region.

Claim 25

The process of claim 21 or 22 characterized in that said first metal is selected from a group consisting of: titanium, vanadium, chromium, zirconium, niobium, molybdenum, hafnium, tantalum, and tungsten.

Claim 26

The process of claim 23 characterized in that said second oxide layer is a reflow oxide material, and wherein said step of depositing a second oxide layer is followed by an additional step of heating the substrate to an elevated temperature to permit saia reflow oxide material to flow.

Claim 27

The process of any one of claims 21-24 characterized in that said first metal is selected from a group consisting of: nickel, palladium, and platinum.

Claim 28

The process of any one of claims 21-25 characterized in that said step of depositing a layer of a first metal is followed by an additional step of implanting silicon into said layer.

Claim 29

The process of any one of claims 21-26 characterized in that said step of depositing a layer of a first metal is additionally operable for depositing said first metal on the upper surfaces of said collector tap and emitter regions, and wherein said silicide also forms upon the upper surfaces of said collector tap ana emitter regions.

Claim 30

The process of any one of claims 21-27 characterized in that said step of forming a first oxide layer comprises the steps of: growing an oxide compound on top of said substrate; and depositing additional oxide material on top of said oxide compound.

Claim 31

The process of any one of claims 21-28 characterized in that said transistor is an n-p-n type transistor, wherein said first conductivity type regions are p-type regions having acceptor impurities, and wherein said second conductivity type regions are n-type regions having donor impurities.

Claim 32

The process of any one of claims 21-29 characterized by a process for forming a Schottky diode, wherein said step of forming a field oxide layer to divide said epitaxial layer into first and second regions is additionally operable for dividing saia epitaxial layer into a third region, wherein said process includes a step of forming an electrical contact on the upper surface of said third region, and wherein said third region and said electrical contact form saia Schottky diode.

Claim 33

The process of any one of claims 21-30 characterized by a process for forming a resistor according to the steps of: forming a third oxide layer on top of said layer of polycrystalline silicon prior to said step of implanting said polycrystalline silicon, wherein said polycrystalline silicon is a lightly doped region of said second conductivity type; removing portions of said third oxide layer to expose regions where implantation is desired, and leaving said third oxide layer over a resistive element region of said polycrystalline silicon; implanting exposed regions of said polycrystalline silicon with impurities of a second type to form said heavily doped layer of said second conductivity type; and selectively removing portions of said exposed regions of said polycrystalline silicon leaving an emitter region positioned above and contacting said base region, leaving a collector tap region above and contacting said second region, and leaving first ana second resistor contacts each coupled to an end of said resistive element region.

Claim 34

The process of any one of claims 21-31 characterized by the steps of: forming a thin insulative layer on top of said base region prior to said step of growing a layer of polycrystalline silicon; and heating said substrate to an elevated temperature after said step of implanting said polycrystalline silicon to diffuse a portion of said impurities of said second type across said thin insulative layer, wherein said emitter region forms a tunnel emitter of said bipolar transistor.