Patent US5366928A successfully refreshed from Google Patents.
US5366928A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a semiconductor device, in which a metal conductor track is provided on a surface of a semiconductor body
Assignee: US Philips Corp
•
Filing: 1993-06-04
•
Granted: 1994-11-22
•
Expires: 2013-06-04
Abstract
Abstract A method of manufacturing a semiconductor device is set forth comprising a semiconductor body (1) having a surface (2) adjoined by a semiconductor region (3) and a field oxide region (4) surrounding this region, on which surface (2) is provided a metal layer (13), in which a conductor track (17, 18) is formed, after which an isolating layer of silicon oxide (19) is deposited over the conductor track (17, 18) on the surface (2). According to the invention, before the layer of silicon oxide (19) is provided over the conductor track (17, 18), this track is provided with a top layer (16) of an oxidation-preventing material. By providing this top layer (16), it is avoided that the conductor track (17, 18) covered by silicon oxide (19) has a high electrical resistance or even an electrical interruption.
Inventors
- 👤 Robertus A. M. Wolters
- 👤 Alexander G. M. Jonkers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:48
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10W; H10W74/00; H10W74/10; H10W74/131; H10D64/0111; H10D64/0112; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; Y; Y10; Y10S; Y10S148/00; Y10S148/015; Y10S438/00; Y10S438/902
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
165 words
A method of manufacturing a semiconductor device comprising the steps of (a) forming a layer of at least one semiconductor region and at least one field oxide region within a semiconductor body, said field oxide region surrounding said semiconductor region, (b) forming conductive tracks from a metal layer formed from a nitrogen-containing alloy of titanium and tungsten in which the atomic ratio of titanium to tungsten is 1:4 and the atomic percent of nitrogen is 10%-30% at a surface of said semiconductor body, said conductive tracks contacting semiconductor regions of said semiconductor body, (c) forming a layer of an oxidation-preventing material of amorphous silicon with a thickness ranging from 3 nm to 50 nm on said conductive tracks to prevent oxidation of said conductive tracks, and (d) thereafter exposing said layer of amorphous silicon to a gas containing silicon and oxygen while heating said body at a temperature above 650° C. to thereby form a layer of silicon oxide on said layer of amorphous silicon.
Claim 2
Independent Claim
165 words
A method of manufacturing a semiconductor device comprising the steps of (a) forming a layer of at least one semiconductor region and at least one field oxide region within a semiconductor body, said field oxide region surrounding said semiconductor region, (b) forming conductive tracks from a metal layer formed from a nitrogen-containing alloy of titanium and tungsten in which the atomic ratio of titanium to tungsten is 1:4 and the atomic percent of nitrogen is 10%-30% at a surface of said semiconductor body, said conductive tracks contacting semiconductor regions of said semiconductor body, (c) forming a layer of an oxidation-preventing material of amorphous silicon with a thickness ranging from 3 nm to 50 nm on said conductive tracks to prevent oxidation of said conductive tracks, and (d) thereafter exposing said layer of amorphous silicon to a gas containing silicon and oxygen while heating said body at a temperature above 650° C. to thereby form a layer of silicon oxide on said layer of amorphous silicon.
Claim 3
Dependent Claim
63 words
A method according to claim 1, wherein said steps (b) and (c) are carried out by depositing said metal layer over said surface of said semiconductor body, by depositing said oxidation-preventing material of amorphous silicon on said metal layer, and by then etching both said metal layer and said oxidation-preventing material into a pattern corresponding to said conductive tracks and said oxidation-preventing material.
Claim 4
Dependent Claim
41 words
A method according to claim 2, wherein said oxidation-preventing material of amorphous silicon is first etched into said pattern, and then said metal layer is etched into said pattern by using the etched pattern of said oxidation-preventing material as a mask.
Claim 5
Dependent Claim
28 words
A method according to claim 2, wherein said semiconductor region is provided at least locally with a top layer of metal silicide before carrying out said step (b).
Claim 6
Dependent Claim
40 words
A method according to claim 4, wherein said top layer of metal silicide is formed by a heat treatment at a temperature lying between 600° and 700° C. for a time of 5 to 20 seconds in a nitrogen-containing atmosphere.
Claim 7
Dependent Claim
28 words
A method according to claim 1, wherein said semiconductor region is provided at least locally with a top layer of metal silicide before carrying out said step (b).
Claim 8
Dependent Claim
40 words
A method according to claim 6, wherein said top layer of metal silicide is formed by a heat treatment at a temperature lying between 600° and 700° C. for a time of 5 to 20 seconds in a nitrogen-containing atmosphere.
Claim 9
Dependent Claim
19 words
A method according to claim 1, wherein said step (c) is carried out at a temperature below 450° C.
Claim 10
Dependent Claim
18 words
A method according to claim 8, wherein said step (c) is carried out by a sputter deposition process.
Claim 11
Dependent Claim
16 words
A method according to claim 8, wherein said step (c) is carried out by vapor deposition.
References Cited (Backward Citations)
US3806361A
Cited
US3859127A
Cited
US4106051A
Cited
US4086613A
Cited
JPS5410668A
Cited
US4267012A
Cited
US4622735A
Cited
JPS5846644A
Cited
JPS5877098A
Cited
JPS58119669A
Cited
US4491860A
Cited
US4558507A
Cited
JPS59111152A
Cited
US4570328A
Cited
US4567058A
Cited
US4624737A
Cited
JPS6189671A
Cited
US4761386A
Cited
EP0190070A2
Cited
US4965218A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-21 | 1998-05-23 | 1998-11-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-21 | 2002-05-23 | 2002-11-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-21 | 2006-05-23 | 2006-11-22 | $7700.00 | Window Closed / Lapsed |