US4965218A
Expired / Lapsed
US
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Self-aligned gate realignment employing planarizing overetch
Assignee: TE Connectivity Solutions GmbH
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Filing: 1988-08-23
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Granted: 1990-10-23
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Expires: 2008-08-23
Abstract
Abstract A method of providing a self-aligned gate (SAG) transistor or FET is disclosed. The method permits large aligment tolerances during manufacture of the SAG FET. A reduction in gate resistance is accomplished by including a second layer of gate metallization, which is highly conductive, after the n+ implant and activation anneal without any critical realignment to the first layer of gate metal. The provision of the second layer after the anneal precludes degradation of the conductivity of the second gate metal by interdiffusion with the first (refractory) gate metal during the anneal. The large tolerance for misalignment of the gate mask level is obtained by a planarization of the anneal cap until the top surface of the first layer of gate metal is exposed, all without the need for a separate mask and etch step to open contact "windows" through the planarization anneal cap layers. The remaining adjacent encapsulant then acts as an insulator over the FET channel region and allows for gross misalignment of the second gate metallization without FET performance degradation. Using this technique, substantially increased performance can be obtained from a self-aligned FET while maintaining the basic simplicity of the RG process.
Inventors
- 👤 Arthur E. Geissberger
- 👤 Robert A. Sadler
- 👤 Paulette Luper
- 👤 Matthew L. Balzan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:59
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/87; H10D30/01; H10D30/061; H10D30/0612; H10D30/0616; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6738; H10D30/674; H10D30/675; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/80; H10D62/85; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; H10D64/0125; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/60; H10D64/64; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D84/02; H10D84/05; H10P; H10P70/00; H10P70/20; H10P70/23; H10P70/234; H10W; H10W20/00; H10W20/01; H10D62/854
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
210 words
A process for the manufacture of self-aligned gate GaAs FET's having reduced gate length and improved gate resistance comprising: (a) providing a substrate; (b) forming a layer of GaAs on said substrate; (c) forming an active channel region in said layer of GaAs; (d) forming a first patterned gate layer comprising a gate of a refractory metal; (e) ion implanting source and drain regions on respective sides of said gate; (f) providing a first dielectric layer over said first patterned gate layer and said source and drain regions; (g) providing a sacrificial layer of etchable material over said first dielectric layer; (h) exposing a top portion of said first patterned gate layer by non-selectively etching said sacrificial layer and said dielectric layer, said top portion having a lateral expanse encompassing said gate; (i) providing a non-critically aligned photoresist mask over the dielectric layer and patterning said photoresist mask to expose said top portion; (j) forming a second gate layer of a material having low sheet resistivity overlying said photoresist mask and directly contacting said top portion through said photoresist mask; and (k) removing said photoresist mask and lifting off said second gate layer overlying said photoresist mask to leave a non-critically aligned second gate layer directly contacting said top portion.
Claim 2
Dependent Claim
210 words
A process for the manufacture of self-aligned gate GaAs FET's having reduced gate length and improved gate resistance comprising: (a) providing a substrate; (b) forming a layer of GaAs on said substrate; (c) forming an active channel region in said layer of GaAs; (d) forming a first patterned gate layer comprising a gate of a refractory metal; (e) ion implanting source and drain regions on respective sides of said gate; (f) providing a first dielectric layer over said first patterned gate layer and said source and drain regions; (g) providing a sacrificial layer of etchable material over said first dielectric layer; (h) exposing a top portion of said first patterned gate layer by non-selectively etching said sacrificial layer and said dielectric layer, said top portion having a lateral expanse encompassing said gate; (i) providing a non-critically aligned photoresist mask over the dielectric layer and patterning said photoresist mask to expose said top portion; (j) forming a second gate layer of a material having low sheet resistivity overlying said photoresist mask and directly contacting said top portion through said photoresist mask; and (k) removing said photoresist mask and lifting off said second gate layer overlying said photoresist mask to leave a non-critically aligned second gate layer directly contacting said top portion.
Claim 3
Dependent Claim
67 words
A process as claimed in claim 1, wherein said step of planarizing said first dielectric layer comprises covering said first dielectric layer with a sacrificial planarization layer; and etching said sacrificial planarization layer and first dielectric layer in an etch environment exhibiting a unity etch ratio with respect to said sacrificial planarization layer and said first dielectric layer to improve the planarity of said first dielectric layer.
Claim 4
Dependent Claim
30 words
A process as claimed in claim 1, wherein said source and drain regions are activated prior to said step of covering said first gate layer with a first dielectric layer.
Claim 5
Dependent Claim
17 words
A process as claimed in claim 1, wherein said second gate layer forms a first level interconnect.
Claim 6
Dependent Claim
185 words
A process for the manufacture of self-aligned gate GaAs FET's having reduced gate length and improved gate resistance comprising: (a) providing a substrate; (b) forming a layer of GaAs on said substrate; (c) forming an active channel region in said layer of GaAs; (d) forming a first patterned gate layer comprising a gate of a refractory metal; (e) ion implanting source and drain regions on respective sides of said gate; (f) providing a first dielectric layer over said first patterned gate layer and said source and drain regions; (g) exposing a top portion of said first patterned gate layer by reactive ion etching of said dielectric layer; (h) providing a non-critically aligned photoresist mask over the dielectric layer and patterning said photoresist mask to expose said top portion; (i) forming a second gate layer of a material having low sheet resistivity overlying said photoresist mask and directly contacting said top portion through said photoresist mask; and (j) removing said photoresist mask and lifting off said second gate layer overlying said photoresist mask to leave a non-critically aligned second gate layer directly contacting said top portion.
Claim 7
Dependent Claim
185 words
A process for the manufacture of self-aligned gate GaAs FET's having reduced gate length and improved gate resistance comprising: (a) providing a substrate; (b) forming a layer of GaAs on said substrate; (c) forming an active channel region in said layer of GaAs; (d) forming a first patterned gate layer comprising a gate of a refractory metal; (e) ion implanting source and drain regions on respective sides of said gate; (f) providing a first dielectric layer over said first patterned gate layer and said source and drain regions; (g) exposing a top portion of said first patterned gate layer by reactive ion etching of said dielectric layer; (h) providing a non-critically aligned photoresist mask over the dielectric layer and patterning said photoresist mask to expose said top portion; (i) forming a second gate layer of a material having low sheet resistivity overlying said photoresist mask and directly contacting said top portion through said photoresist mask; and (j) removing said photoresist mask and lifting off said second gate layer overlying said photoresist mask to leave a non-critically aligned second gate layer directly contacting said top portion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |