Self-aligned fabrication process for GaAs MESFET devices

Claim 1

A self-aligned process for fabricating a semiconductor MESFET device comprising the steps of: providing a semiconductor substrate; depositing a layer of tungsten over said substrate; ion implanting said substrate with a dopant species through said layer of tungsten to provide channel doping; depositing a platinum-gold layer; depositing a masking layer over said platinum-gold layer; patterning said platinum-gold layer defined by said masking layer to form a gate etch mask; forming source and drain regions in said substrate using said gate etch mask as a mask; annealing said device; selectively removing portions of said tungsten layer to form a gate using said gate etch mask region as a mask; and forming electrical contacts to said source region, to said drain region, and to said gate.