EP0190070A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor structure
Assignee: Fairchild Semiconductor Corp
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Filing: 1986-01-16
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Granted: —
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Expires: 2006-01-16
Abstract
Abstract An improved MOS transistor construction utilizes a polysilicon gate covered by silicide and silicide covered, self-aligned source and drain regions separated from the gate polysilicon by thin silicon dioxide spacers. No contact windows are formed within the perimeter of the isolation island. This allows for very small geometries. Electrical contact to the source and drain regions is provided by a conductive pattern formed in a layer of refractory metal which is in electrical contact with the source, drain and gate silicide and which extends over the field oxide to contact pad positions outside the isolation islands of the transistors. The contact pads located outside the isolation islands support post type vias or contact windows. The posts can be formed of different heights so that electrical contact by first and second metal layers to the source, gate and drain regions of the device can be made with the first and second metal layers separated by intermetal insulation. A process is disclosed for making high performance bipolar and high performance MOS devices on the same integrated circuit die which comprises forming isolation islands of epitaxial silicon surrounded by field oxide and forming MOS transistors having polysilicon gates in some islands and forming bipolar transistors having polysilicon emitters in other islands. Insulating spacers are then formed around the edges of the polysilicon electrodes by anisotropically etching a layer of insulation material. A layer of refractory metal is then deposited and heat treated at a temperature high enough to form silicide over the tops of the polysilicon electrodes and on top of the bases, sources and drains. Regions of this refractory metal are then masked off such that the electrical contact with the silicide is preserved and so that the refractory metal extends to a contact pad position external to the isolation island. Metal posts can be formed at the contact pad positions and a layer of planarized insulation material is formed so as to leave only the tops of the posts exposed. A layer of metal can then be deposited and etched to make electrical contact with tops of the posts. There is also disclosed a dynamic RAM cell using an MOS transistor and a CMOS static RAM cell comprising six MOS transistors having source, drain and gate electrodes which are smaller than the smallest contact window which can be made by the process which was used to make the transistor.
Inventors
- 👤 Madhukar Vora
- 👤 Greg Burton
- 👤 Ashok Kapoor
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 21:55
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10B; H10B10/00; H10B10/12; H10B12/00; H10B12/30; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D84/02; H10D84/03; H10D84/038; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/063; H10W20/064; H10W20/066; H10W20/0698; H10W20/40; H10W20/41; H10W20/43; H10W20/44; H10W20/4451
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
40 words
A transistor characterized by a source, a drain, a gate and gate insulation material all formed within an isolation island of conductive silicon surrounded by field oxide but not having any contact window within the perimeter of said isolation island.
Claim 2
Dependent Claim
40 words
A transistor characterized by a source, a drain, a gate and gate insulation material all formed within an isolation island of conductive silicon surrounded by field oxide but not having any contact window within the perimeter of said isolation island.
Claim 3
Dependent Claim
17 words
The transistor of claim 1 characterized by silicide layers on top of said source, drain ana gate.
Claim 4
Dependent Claim
24 words
The transistor of claim 1 or 2 characterized by refractory metal overlying said field oxide and in electrical contact with selected regions of silicide.
Claim 5
Dependent Claim
130 words
A semiconductor structure characterized by: a semiconductor substrate doped with a first type impurity having formed thereon an epitaxial layer of semiconductor doped with impurities of a second type, a portion of said epitaxial layer being electrically isolated from surrounding portions in that there are no current paths to surrounding portions of said epitaxial layer through said epitaxial layer; an emitter region in said isolated portions of said epitaxial layer; an emitter contact electrically coupled to said emitter region; a silicide case tap in electrical contact with any portion of said isolated region of said epitaxial layer not within said emitter region; a first conductor in electrical contact with said silicide base tap and extending to a case contact window region external to said isolated portion of said epitaxial layer.
Claim 6
Dependent Claim
130 words
A semiconductor structure characterized by: a semiconductor substrate doped with a first type impurity having formed thereon an epitaxial layer of semiconductor doped with impurities of a second type, a portion of said epitaxial layer being electrically isolated from surrounding portions in that there are no current paths to surrounding portions of said epitaxial layer through said epitaxial layer; an emitter region in said isolated portions of said epitaxial layer; an emitter contact electrically coupled to said emitter region; a silicide case tap in electrical contact with any portion of said isolated region of said epitaxial layer not within said emitter region; a first conductor in electrical contact with said silicide base tap and extending to a case contact window region external to said isolated portion of said epitaxial layer.
Claim 7
Dependent Claim
36 words
A vertical bipolar transistor characterizea by its base contact window located outside the perimeter of the base region isolation island and having a conductor coupling said base contact window to the base region of the transistor.
Claim 8
Dependent Claim
36 words
A vertical bipolar transistor characterizea by its base contact window located outside the perimeter of the base region isolation island and having a conductor coupling said base contact window to the base region of the transistor.
Claim 9
Dependent Claim
115 words
A process for forming an external base contact for a bipolar transistor having a base region formed in an island of semiconductor material which is electrically isolated from its surrounding semiconductor material characterized by tne steps of: forming a layer ot metal over the exposed silicon of said base region; heat treating said metal to form silicide which is self aligned with the perimeter of said base region; forming an etch protection layer overlapping the edge of said silicide aligned with the edge of said isolation island and the portion of said metal layer adjacent to said edge and in electrical contact with said silicide; etching away portions of said metal layer not so protected.
Claim 10
Dependent Claim
115 words
A process for forming an external base contact for a bipolar transistor having a base region formed in an island of semiconductor material which is electrically isolated from its surrounding semiconductor material characterized by tne steps of: forming a layer ot metal over the exposed silicon of said base region; heat treating said metal to form silicide which is self aligned with the perimeter of said base region; forming an etch protection layer overlapping the edge of said silicide aligned with the edge of said isolation island and the portion of said metal layer adjacent to said edge and in electrical contact with said silicide; etching away portions of said metal layer not so protected.
Claim 11
Dependent Claim
86 words
A static RAM cell characterized by: six MOS transistors having source, drain and gate electrodes with layers of siliciae overlying said electrodes; refractory metal and said silicide electrically connecting the drains of the first and third transistors to the gates of the second and fourth transistors and to the source of the fifth transistor; refractory metal and said silicide electrically connecting the arains of the second and fourth transistors to the gates of the first and third transistors and to the source of the sixth transistor.
Claim 12
Dependent Claim
86 words
A static RAM cell characterized by: six MOS transistors having source, drain and gate electrodes with layers of siliciae overlying said electrodes; refractory metal and said silicide electrically connecting the drains of the first and third transistors to the gates of the second and fourth transistors and to the source of the fifth transistor; refractory metal and said silicide electrically connecting the arains of the second and fourth transistors to the gates of the first and third transistors and to the source of the sixth transistor.
Claim 13
Dependent Claim
102 words
A dynamic RAM cell integrated in a substrate characterized by: an MOS transistor having source and drain regions in said substrate and having a gate electrode, each of said source and drain regions and said gate electrode having silicide overlying it and further comprising insulating spacers insulating the silicide overlying said source and drain regions from the gate electrode; a capacitor comprising a first conductor, a second conductor formed in said substrate and a layer of insulation insulating said conductors from each other; and wherein said source region is self aligned with the edge of and electrically coupled to said second conductor.
Claim 14
Dependent Claim
102 words
A dynamic RAM cell integrated in a substrate characterized by: an MOS transistor having source and drain regions in said substrate and having a gate electrode, each of said source and drain regions and said gate electrode having silicide overlying it and further comprising insulating spacers insulating the silicide overlying said source and drain regions from the gate electrode; a capacitor comprising a first conductor, a second conductor formed in said substrate and a layer of insulation insulating said conductors from each other; and wherein said source region is self aligned with the edge of and electrically coupled to said second conductor.
Claim 15
Dependent Claim
107 words
An MOS transistor characterized by: an island of first conductivity type silicon surrounded by field oxide; a layer of gate insulator overlying a portion of said island; second conductive silicon overlying said gate insulation material; first silicide overlying said second conductive silicon; insulating spacer material insulating at least the sides of said second conductive silicon; source and drain regions in said first conauctivity type silicon doped to a second conductivity type as that of saia first conductivity type silicon; second silicide covering at least a portion of said source and drain regions; and refractory metal overlying said field oxide and in electrical contact with saia second silicide.
Claim 16
Dependent Claim
107 words
An MOS transistor characterized by: an island of first conductivity type silicon surrounded by field oxide; a layer of gate insulator overlying a portion of said island; second conductive silicon overlying said gate insulation material; first silicide overlying said second conductive silicon; insulating spacer material insulating at least the sides of said second conductive silicon; source and drain regions in said first conauctivity type silicon doped to a second conductivity type as that of saia first conductivity type silicon; second silicide covering at least a portion of said source and drain regions; and refractory metal overlying said field oxide and in electrical contact with saia second silicide.
Claim 17
Dependent Claim
180 words
A process for making high performance bipolar and high performance MOS devices on the same die characterized by the steps of: forming a plurality of islands of silicon of a first conductivity type surrounded by an insulating material of a lower conductivity; doping selected islands to a second conductivity type; forming a layer of gate oxide over selected islands to contain MOS devices; depositing polysilicon over all islands; doping the polysilicon in selected regions with an impurity of a first conductivity type; etching said polysilicon into predetermined electrode patterns; doping the exposed portions of selected islands with an impurity of a type to form source and drain regions of said second conductivity type; forming a layer of insulation material over the structure; anisotropically etching said insulation material to form insulating spacers on predetermined surfaces of said polysilicon electrodes; forming a layer of refractory metal over the structure; heat treating to form silicide over all exposed silicon and polysilicon but not over insulation material; masking selected areas of the refractory metal and silicide; and etching off all refractory metal not masked.
Claim 18
Dependent Claim
180 words
A process for making high performance bipolar and high performance MOS devices on the same die characterized by the steps of: forming a plurality of islands of silicon of a first conductivity type surrounded by an insulating material of a lower conductivity; doping selected islands to a second conductivity type; forming a layer of gate oxide over selected islands to contain MOS devices; depositing polysilicon over all islands; doping the polysilicon in selected regions with an impurity of a first conductivity type; etching said polysilicon into predetermined electrode patterns; doping the exposed portions of selected islands with an impurity of a type to form source and drain regions of said second conductivity type; forming a layer of insulation material over the structure; anisotropically etching said insulation material to form insulating spacers on predetermined surfaces of said polysilicon electrodes; forming a layer of refractory metal over the structure; heat treating to form silicide over all exposed silicon and polysilicon but not over insulation material; masking selected areas of the refractory metal and silicide; and etching off all refractory metal not masked.
Claim 19
Dependent Claim
54 words
An interconnection for an integrated circuit characterized by a layer of refractory metal overlying a region of insulation material and merging with a layer of silicide formed in a region of silicon bounded by said insulating material wherein said refractory metal turns into siliciae at the boundary of said silicon and said insulating material.
Claim 20
Dependent Claim
54 words
An interconnection for an integrated circuit characterized by a layer of refractory metal overlying a region of insulation material and merging with a layer of silicide formed in a region of silicon bounded by said insulating material wherein said refractory metal turns into siliciae at the boundary of said silicon and said insulating material.
References Cited (Backward Citations)
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