Insulated gate bipolar transistor having high short-circuit SOA and high latch-up current

Claim 2

An insulated gate bipolar transistor, comprising: a first conductivity type first semiconductor layer having first and second major surfaces; a second conductivity type second semiconductor layer formed on said first major surface of said first semiconductor layer; a first conductivity type first semiconductor region selectively formed in a surface of said second semiconductor layer; a plurality of second conductivity type second semiconductor regions selectively formed in a surface of said first semiconductor region; portions of said first semiconductor region, in a peripheral portion of said first semiconductor region, near a portion of the surface of said first semiconductor region between ends of surfaces of said first semiconductor region between ends of surfaces of said first and second semiconductor regions being defined as channel regions; a distance D between said second semiconductor regions and a length L of said channel region which is defined as a distance between the ends of the surfaces of said first and second semiconductor regions satisfying D>2L; an insulation film formed on said channel region; a control electrode formed on said insulation film; a first main electrode formed on said first and second semiconductor regions; and a second main electrode formed on said second major surface of said first semiconductor layer; wherein a value E c per unit area of a calorific energy of said insulated gate bipolar transistor satisfies E c <5 Joules/cm 2 .

Claim 3

An insulated gate bipolar transistor in accordance with claim 1, wherein said insulated gate bipolar transistor consists of a plurality of cells connected in parallel, and said first semiconductor region is formed in the shape of a strip and is provided for each of said cells.

Claim 4

An insulated gate bipolar transistor in accordance with claim 2, wherein said distance D and a thickness X of said second semiconductor layer under said first semiconductor region satisfies D>2X.

Claim 5

An insulated gate bipolar transistor in accordance with claim 2, further comprising; a first conductivity type high concentration region formed at least in a portion of the surface of said first semiconductor region between said second semiconductor regions, having an impurity concentration sufficiently higher than said first semiconductor region, being closer to an end portion of said first semiconductor region than said second semiconductor regions between said second semiconductor regions.

Claim 6

An insulated gate bipolar transistor in accordance with claim 2, wherein said insulated gate bipolar transistor has a breakdown voltage of about 500 to 750 volts, and a value W U per unit area of a width of said channel region, which is defined as a length along opposite ends of the surfaces of said first and second semiconductor regions, satisfying 140 cm -1 ≦W U ≦280 cm -1 .

Claim 7

An insulated gate bipolar transistor in accordance with claim 5, wherein said insulated gate bipolar transistor has a breakdown voltage of about 1000 to 1500 volts, and a value W U per unit area of a width of said channel region, which is defined as a length along opposite ends of the surfaces of said first and second semiconductor regions, satisfying 70 cm -1 ≦W U ≦150 cm -1 .

Claim 8

An insulated gate bipolar transistor in accordance with claim 1, further comprising; a plurality of second conductivity type third semiconductor regions intermittently formed in said first semiconductor layer so as to penetrate said first semiconductor layer.

Claim 9

An insulated gate bipolar transistor, comprising: a first conductivity type first semiconductor layer having first and second major surfaces; a second conductivity type second semiconductor layer formed on said first major surface of said first semiconductor layer; a first conductivity type first semiconductor region selectively formed in a surface of said second semiconductor layer; a plurality of second conductivity type second semiconductor regions selectively formed in a surface of said first semiconductor region, portions of said first semiconductor region, in a peripheral portion of said first semiconductor region, near a portion of the surface of said first semiconductor region between ends of surfaces of said first and second semiconductor regions being defined as channel regions; a first conductivity type high concentration region formed at least in a portion of the surface of said first semiconductor region between said second semiconductor regions, having an impurity concentration sufficiently higher than said first semiconductor region, being closer to an end portion of said first semiconductor region than said second semiconductor regions in portions between said second semiconductor regions; an insulation film formed on said channel region; a control electrode formed on said insulation film; a first main electrode formed on said first and second semiconductor regions; and a second main electrode formed on said second major surface of said first semiconductor layer; wherein a distance D between said second semiconductor regions and a length L of said channel region which is defined as a distance between the ends of the surfaces of said first and second semiconductor regions satisfies D>2L; wherein a value E c per unit area of a calorific energy of said insulated gate bipolar transistor satisfies E c <5 Joules/cm 2 .

Claim 10

An insulated gate bipolar transistor, comprising: a first conductivity type first semiconductor layer having first and second major surfaces; a second conductivity type second semiconductor layer formed on said first major surface of said first semiconductor layer; a first conductivity type first semiconductor region selectively formed in a surface of said second semiconductor layer; a plurality of second conductivity type second semiconductor regions selectively formed in a surface of said first semiconductor region, portions of said first semiconductor region, in a peripheral portion of said first semiconductor region, near a portion of the surface of said first semiconductor region between ends of surfaces of said first and second semiconductor regions being defined as channel regions; a first conductivity type high concentration region formed at least in a portion of the surface of said first semiconductor region between said second semiconductor regions, having an impurity concentration sufficiently higher than said first semiconductor region, being closer to an end portion of said first semiconductor region than said second semiconductor regions in portions between said second semiconductor regions; an insulation film formed on said channel region; a control electrode formed on said insulation film; a first main electrode formed on said first and second semiconductor regions; and a second main electrode formed on said second major surface of said first semiconductor layer; wherein a distance D between said second semiconductor regions and a length L of said channel region which is defined as a distance between the ends of the surfaces of said first and second semiconductor regions satisfies D>2L; wherein a value E c per unit area of a calorific energy of said insulated gate bipolar transistor satisfies E c <5 Joules/cm 2 .