Patent US5049765A successfully refreshed from Google Patents.
US5049765A
Expired / Lapsed
US
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BiCMOS noninverting buffer and logic gates
Assignee: Intel Corp
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Filing: 1990-06-19
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Granted: 1991-09-17
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Expires: 2010-06-19
Abstract
Abstract A BiCMOS logic circuit which implements single stage noninverting logic functions is described. The circuit includes pull-up and pull-down assembly means coupled between the input and output nodes. The pull-down assemby means comprises a pair of complimentary metal-oxide semiconductor field-effect transistors connected in an inverter configuration in which the gates of the pair of CMOS transistors are coupled to the input node while the output of the inverter configuration drives the base of a bipolar transistor coupled to the output node.
Inventors
- 👤 Ian A. Young
- 👤 Jeffrey K. Greason
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:45
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
120 words
A BiCMOS binary logic circuit implementing an OR function comprising: a plurality of emitter follower transistors, each having a base coupled to corresponding inputs of said circuit, said emitter follower transistors having their emitters commonly coupled to an output node; a pull-down circuit means including a plurality of complementary MOS transistors connected in a CMOS NOR configuration wherein the gates of pairs of said complementary MOS transistors are coupled to said corresponding inputs and the output of said NOR configuration is coupled to the base of a bipolar transistor, for sinking current from said output node through said bipolar transistor to pull the potential of said output node low when all of said inputs are driven with a low potential.
Claim 2
Dependent Claim
120 words
A BiCMOS binary logic circuit implementing an OR function comprising: a plurality of emitter follower transistors, each having a base coupled to corresponding inputs of said circuit, said emitter follower transistors having their emitters commonly coupled to an output node; a pull-down circuit means including a plurality of complementary MOS transistors connected in a CMOS NOR configuration wherein the gates of pairs of said complementary MOS transistors are coupled to said corresponding inputs and the output of said NOR configuration is coupled to the base of a bipolar transistor, for sinking current from said output node through said bipolar transistor to pull the potential of said output node low when all of said inputs are driven with a low potential.
Claim 3
Dependent Claim
13 words
The circuit of claim 1 wherein said bipolar transistor comprises an NPN transistor.
Claim 4
Dependent Claim
56 words
The circuit of claim 2 wherein said circuit implements a two-input OR function and said plurality of complementary MOS transistors comprise a pair of p-channel MOS transistors coupled in series across the base-collector junction of said bipolar transistor and a pair of n-channel MOS transistors connected in parallel across the base-emitter junction of said bipolar transistor.
Claim 5
Dependent Claim
117 words
A BiCMOS binary logic circuit implementing a logical sum operation comprising: a plurality of emitter follower transistors, each having a base coupled to corresponding inputs, said emitter follower transistors having their emitters commonly coupled to an output node; a pull-down circuit means including a plurality of complementary MOS transistors connected in a CMOS NOR configuration, wherein gates of pairs of said complementary MOS transistors are coupled to said corresponding inputs and the output of said NOR configuration is coupled to the gate of an NMOS transistor, for sinking current from said output node through said NMOS transistor to pull the potential of said output node low when all of said inputs are driven with a low potential.
Claim 6
Dependent Claim
117 words
A BiCMOS binary logic circuit implementing a logical sum operation comprising: a plurality of emitter follower transistors, each having a base coupled to corresponding inputs, said emitter follower transistors having their emitters commonly coupled to an output node; a pull-down circuit means including a plurality of complementary MOS transistors connected in a CMOS NOR configuration, wherein gates of pairs of said complementary MOS transistors are coupled to said corresponding inputs and the output of said NOR configuration is coupled to the gate of an NMOS transistor, for sinking current from said output node through said NMOS transistor to pull the potential of said output node low when all of said inputs are driven with a low potential.
Claim 7
Dependent Claim
56 words
The circuit of claim 4 wherein said plurality of complementary MOS transistors comprise a pair of p-channel MOS transistors coupled in series between a first supply potential and the gate of said NMOS transistor, and a pair of n-channel MOS transistors connected in parallel between the gate of said NMOS transistor and a second supply potential.
Claim 8
Dependent Claim
22 words
The circuit of claim 5 wherein said first supply potential comprises a high positive potential and said second supply potential comprises ground.
Claim 9
Dependent Claim
55 words
The circuit of claim 5 wherein the output of said NOR configuration is coupled to the base of a bipolar transistor having its emitter coupled to the gate of said NMOS transistor and its collector coupled to said first supply potential, said bipolar transistor providing faster switching when said circuit draws relatively large capacitive loads.
Claim 10
Dependent Claim
44 words
The circuit of claim 7 further comprising another pair of n-channel MOS transistors connected in parallel between the emitter of said bipolar transistor and said second supply potential, the gates of said another pair of n-channel MOS transistors being coupled to said corresponding inputs.
Claim 11
Dependent Claim
22 words
The circuit of claim 8 wherein said first supply potential comprises a high positive potential in said second supply potential comprises ground.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-16 | 1995-03-18 | 1995-09-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-16 | 1999-03-18 | 1999-09-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-16 | 2003-03-18 | 2003-09-17 | $7700.00 | Window Closed / Lapsed |