US4871928A
Expired / Lapsed
US
⏱️ 0.0 years remaining
BICMOS driver circuit with complementary outputs
Assignee: Motorola Solutions Inc
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Filing: 1988-08-23
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Granted: 1989-10-03
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Expires: 2008-08-23
Abstract
Abstract A BICMOS inverter circuit having a high input impedance, improved switching characteristics, low power requirements, high noise immunity, high drive capability, an increased output voltage swing, reduced body effect, high current drivability and improved power dissipation comprises a CMOS inverter for receiving an input signal and bipolar push-pull output transistors for supplying an output. An intermediate CMOS stage is coupled between the CMOS inverter and the bipolar push-pull output transistors and to power supply voltages in a manner that eliminates body effect.
Inventors
- 👤 Thomas P. Bushey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 07:32
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/151; H03K19/00; H03K19/01; H03K19/013; H03K19/0136; H03K19/0175; H03K19/017509; H03K19/017518; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
219 words
A circuit comprising: a first supply voltage terminal; a second supply voltage terminal an input terminal; a first output terminal; a first bipolar transistor coupled between said first supply voltage terminal and said first output terminal; a second bipolar transistor coupled between said first output terminal and said second supply voltage terminal; first means coupled between said first and second supply voltage terminals and having an input coupled to said input terminal and an output coupled to a base of said first bipolar transistor and said second bipolar transistor for providing a voltage for biasing said first and second transistors, said first means providing a high impedance to said input terminal; second means coupled between said first and second supply voltage terminals and having an input coupled to said input terminal and an output coupled to said output terminal for providing a voltage at said first output terminal that varies in magnitude from the voltage on said first and second supply voltage terminals in response to an input signal on said input terminal, said second means providing a high impedance to said input terminal; and third means coupled between said first and second supply voltage terminals and having an input coupled to said first output terminal and an output coupled to said second means for biasing said second means.
Claim 2
Dependent Claim
219 words
A circuit comprising: a first supply voltage terminal; a second supply voltage terminal an input terminal; a first output terminal; a first bipolar transistor coupled between said first supply voltage terminal and said first output terminal; a second bipolar transistor coupled between said first output terminal and said second supply voltage terminal; first means coupled between said first and second supply voltage terminals and having an input coupled to said input terminal and an output coupled to a base of said first bipolar transistor and said second bipolar transistor for providing a voltage for biasing said first and second transistors, said first means providing a high impedance to said input terminal; second means coupled between said first and second supply voltage terminals and having an input coupled to said input terminal and an output coupled to said output terminal for providing a voltage at said first output terminal that varies in magnitude from the voltage on said first and second supply voltage terminals in response to an input signal on said input terminal, said second means providing a high impedance to said input terminal; and third means coupled between said first and second supply voltage terminals and having an input coupled to said first output terminal and an output coupled to said second means for biasing said second means.
Claim 3
Dependent Claim
69 words
The circuit according to claim 1 further comprising: a second output terminal; a third bipolar transistor coupled between said first supply voltage terminal and said second output terminal, and having a base coupled to said output of said third means; and a fourth bipolar transistor coupled between said second output terminal and said second supply voltage terminal, and having a base coupled to said output of said third means.
Claim 4
Dependent Claim
75 words
The circuit according to claim 1 wherein said second means comprises: a first CMOS transistor having a source coupled to said first supply voltage terminal, a drain coupled to said first output terminal, and a gate coupled to said output of said third means; and a second CMOS transistor having a source coupled to said second supply voltage terminal, a drain coupled to said first output terminal, and a gate coupled to said input terminal.
Claim 5
Dependent Claim
80 words
The circuit according to claim 3 wherein said third means comprises: a third CMOS transistor having a source coupled to said first supply voltage terminal, a drain coupled to said gate of said first CMOS transistor, and a gate coupled to said first output terminal; and a fourth CMOS transistor having a source coupled to said second supply voltage terminal, a drain coupled to said gate of said first CMOS transistor, and a gate coupled to said first output terminal.
Claim 6
Dependent Claim
82 words
The circuit according to claim 4 wherein said first means comprises: a fifth CMOS transistor having a source coupled to said first supply voltage terminal, a drain coupled to said bases of said first and second bipolar transistors, and a gate coupled to said input terminal; and a sixth CMOS transistor having a source coupled to said second supply voltage terminal, a drain coupled to said bases of said first and second bipolar transistors, and a gate coupled to said input terminal.
Claim 7
Dependent Claim
75 words
The circuit according to claim 5 further comprising: a second output terminal; a third bipolar transistor coupled between said first supply voltage terminal and said second output terminal, and having a base coupled to the drains of said third and fourth CMOS transistors; and a fourth bipolar transistor coupled between said second output terminal and said second supply voltage terminal, and having a base coupled to the drains of said third and fourth CMOS transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-02 | 1993-04-03 | 1993-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-02 | 1997-04-03 | 1997-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-02 | 2001-04-03 | 2001-10-03 | $7700.00 | Window Closed / Lapsed |