Merged PMOS/bipolar logic circuits

Claim 2

An inverter circuit formed of merged P-channel MOS transistors and bipolar transistors to produce a single logic gate comprising: a first P-channel MOS transistor having its gate connected to an input terminal and its source connected to a supply potential; a first bipolar transistor having its collector connected to the supply potential, its base connected to the drain of said first P-channel transistor, and its emitter connected to an output terminal; a first resistor having its one end connected to the drain of said first P-channel transistor and to the base of said first bipolar transistor, the other end of said first resistor being connected to the emitter of said first bipolar transistor and to the output terminal; a second P-channel MOS transistor having its gate and source connected together and its drain connected to the gate of said first P-channel transistor and to the input terminal; a second bipolar transistor having its collector connected to the output terminal, its base connected to the gate and source of said second P-channel transistor, and its emitter connected to a ground potential; and a second resistor having its one end connected to the base of said second bipolar transistor and its other end connected to the emitter of said second bipolar transistor.

Claim 3

An inverter circuit as claimed in claim 1, wherein said first bipolar transistor is of a NPN-type conductivity.

Claim 4

An inverter circuit as claimed in claim 1, wherein said second bipolar transistor is of a NPN-type conductivity.

Claim 5

An inverter circuit as claimed in claim 3, wherein said second bipolar transistor comprises a Schottky transistor.

Claim 6

An inverter circuit as claimed in claim 1, wherein said inverter circuit is formed on a single silicon chip of an integrated circuit.

Claim 7

A NOR circuit formed of merged P-channel MOS transistors and bipolar transistors to produce a single logic gate comprising: a first P-channel MOS transistor having its gate connected to a first input terminal; a first bipolar transistor having its collector connected to a supply potential, its base connected to the drain of said first P-channel transistor, and its emitter connected to an output terminal; a first resistor having its one end connected to the drain of said first P-channel transistor and to the base of said first bipolar transistor, the other end of said first resistor being connected to the emitter of said first bipolar transistor and to the output terminal; a second P-channel MOS transistor having its gate and source connected together and its drain connected to the gate of said first P-channel transistor and to the first input terminal; a second bipolar transistor having its collector connected to the output terminal, its base connected to the gate and source of said second P-channel transistor, and its emitter connected to a ground potential; a second resistor having its one end connected to the base of said second bipolar transistor and its other end connected to the emitter of said second bipolar transistor; a third P-channel MOS transistor having its gate connected to a second input terminal, its source connected to the supply potential, and its drain connected to the source of said first P-channel transistor; and a fourth P-channel MOS transistor having its gate and source connected together and to the base of said second bipolar transistor, the drain of said fourth P-channel transistor being connected to the gate of said third P-channel transistor and to the second input terminal.

Claim 8

A NOR circuit formed of merged P-channel MOS transistors and bipolar transistors to produce a single logic gate comprising: a first P-channel MOS transistor having its gate connected to a first input terminal; a first bipolar transistor having its collector connected to a supply potential, its base connected to the drain of said first P-channel transistor, and its emitter connected to an output terminal; a first resistor having its one end connected to the drain of said first P-channel transistor and to the base of said first bipolar transistor, the other end of said first resistor being connected to the emitter of said first bipolar transistor and to the output terminal; a second P-channel MOS transistor having its gate and source connected together and its drain connected to the gate of said first P-channel transistor and to the first input terminal; a second bipolar transistor having its collector connected to the output terminal, its base connected to the gate and source of said second P-channel transistor, and its emitter connected to a ground potential; a second resistor having its one end connected to the base of said second bipolar transistor and its other end connected to the emitter of said second bipolar transistor; a third P-channel MOS transistor having its gate connected to a second input terminal, its source connected to the supply potential, and its drain connected to the source of said first P-channel transistor; and a fourth P-channel MOS transistor having its gate and source connected together and to the base of said second bipolar transistor, the drain of said fourth P-channel transistor being connected to the gate of said third P-channel transistor and to the second input terminal.

Claim 9

A NOR circuit as claimed in claim 6, wherein said first bipolar transistor is of a NPN-type conductivity.

Claim 10

A NOR circuit as claimed in claim 6, wherein said second bipolar transistor is of a NPN-type conductivity.

Claim 11

A NOR circuit as claimed in claim 8, wherein said second bipolar transistor comprises a Schottky transistor.

Claim 12

A NOR circuit as claimed in claim 6, wherein said NOR circuit is formed on a single silicon chip of an integrated circuit.