Semiconductor integrated circuit device

Abstract

Abstract PURPOSE:To obtain a rapid logical circuit with low power consumption by utilizing the merit of CMOS element and bipolar element. CONSTITUTION:When an input 16 is the ''0'' level, a MOS 10 is turned on, the 1st NMOS 11 is turned off and the 1st npn bipolar element 14 is also turned on. On the other hand, the 2nd npn bipolar element 15 is turned off by shorting between the base and emitter through the 3rd NMOS 13 included in a non- saturated area, so that the emitter current of the 1st npn element 14 charges a load and the output 17 is turned to the logical ''1'' level. When the input 16 is turned to ''1'' level on the contrary, the PMOS 10 is turned off and the 1st NMOS 11 is turned on. Therefore, the 1st npn element 14 is turned off because the part between the base and emitter is shorted through the 2nd NMOS 12 included in the non-saturated area, so that current is supplied to the base of the 2nd npn element 15 from the output 17 to turn on the element 15, and the output 17 is reduced to ''0'' level.

Inventors

• 👤 Yoji Nishio
• 👤 洋二 西尾
• 👤 Ikuro Masuda
• 👤 郁朗 増田
• 👤 Kazuo Kato
• 👤 和男 加藤
• 👤 Shigeo Kuboki
• 👤 茂雄 久保木
• 👤 Masahiro Iwamura
• 👤 将弘 岩村

Bibliographic Details