Logic circuit and semiconductor integrated circuit device capable of operating by different power supplies

Claim 2

A logic circuit comprising: a selection signal generation circuit for generating a selection signal selecting one of a plurality of power supply potentials; a power supply potential selection circuit for selecting one of said power supply potentials on the basis of said selection signal; a first semiconductor switch circuit for forming a first current path from said selected power supply to an output terminal connected to a capacitance load in response to at least one input signal; and a second semiconductor switch circuit for forming a second current path from said output terminal to a power supply potential, which is not said selected power supply potential, in response to at least one input signal, said second semiconductor switch circuit being not turned ON simultaneously with said first semiconductor switch circuit under the steady state.

Claim 3

A logic circuit according to claim 1, wherein said selection signal generation circuit generates said selection signal on the basis of a signal applied thereto from a source external to the logic circuit.

Claim 4

A logic circuit according to claim 2, wherein said selection signal generation circuit holds a signal applied thereto from the external source for a predetermined period of time and genrerates said selection signal corresponding to said signal applied thereto from outside.

Claim 5

A logic circuit according to claim 1, wherein said power supply potential selection circuit selects one of two power supply potentials.

Claim 6

A logic circuit according to claim 4, wherein said power supply potential selection circuit consists of a third semiconductor switch circuit for selecting one of said two power supply potentials in response to said selection signal and a fourth semiconductor switch circuit for selecting the other of said two power supply potentials in response to the inversed signal of said selection signal.

Claim 7

A logic circuit according to claim 4, wherein said power supply potential selection circuit consists of a third semiconductor switch circuit for selecting one of said two power supply potentials in response to said selection signal and a fourth semiconductor switch circuit for selecting the other of said two power source potentials by operating complementary to said third semiconductor switch circuit in response to said selection signal.

Claim 8

A logic circuit according to claim 1, wherein said power supply potential selection circuit selects one of said power supply potentials from a predetermined junction of means for distributing voltage connected between a pair of power supply potentials.

Claim 9

A logic circuit according to claim 1, wherein said first semiconductor switch circuit consists of at least one field effect transistor whose gate is connected to said at least one of said input signals and whose source-drain current path forms said first current path.

Claim 10

A logic circuit according to claim 8, wherein said at least one field effect transistor is a field effect transistor having a first conductivity type.

Claim 11

A logic circuit according to claim 1, wherein said second semiconductor switch circuit consists of at least one field effect transistor whose gate is connected to at least one input signal and whose source-drain current path forms said second current path.

Claim 12

A logic circuit according to claim 10, wherein said at least one field effect transistor is a field effect transistor having a second conductivity type.

Claim 13

A logic circuit according to claim 1, wherein said first semiconductor switch circuit consists of at least one bipolar transistor whose collector-emitter current path forms said first current path; at least one field effect transistor whose gate is connected to at least one input signal and whose source-drain current path forms a current path from said selected power supply potential to the base of said at least one bipolar transistor; and a semiconductor device connected to the base of said at least one bipolar transistor and withdrawing the charge stored at said base.

Claim 14

A logic circuit according to claim 12, wherein said at least one bipolar transistor is a bipolar transistor having the base of a first conductivity type and the collector and emitter having a second conductivity type, and said at least one field effect transistor is a field effect transistor having said first conductivity type.

Claim 15

A logic circuit according to claim 1, wherein said second semiconductor switch circuit consists of at least one bipolar transistor whose collector-emitter current path forms said second current path; at least one field effect transistor whose gate is connected to at least one input signal and whose source-drain current path forms a current path from said output terminal to the base of said at least one bipolar transistor; and a semiconductor device connected to the base of said at least one bipolar transistor and withdrawing the charge stored at said base.

Claim 16

A logic circuit according to claim 14, wherein said at least one bipolar transistor is a bipolar transistor having the base of a first conductivity type and the collector and emitter of a second conductivity type, and said at least one field effect transistor is a field effect transistor of the second conductivity type.

Claim 17

In a semiconductor integrated circuit device of the type wherein an input buffer circuit for inputting an external signal, an internal circuit for exhibiting a predetermined functional operation on the basis of the signal from said input buffer circuit and an output buffer circuit for outputting the output signal of said internal circuit to an external element are integrated on the same semiconductor substrate, the improvement wherein said output buffer circuit comprises: a selection signal generation circuit for generating a selection signal for selecting one of a plurality of power supply potentials; a power supply potential selection circuit for selecting one of said power supply potentials on the basis of said selection signal; a first semiconductor switch circuit for forming a first current path from said selected power supply potential to the output terminal to be connected to said external element in response to the output signal of at least one of said internal circuits; and a second semiconductor switch circuit for forming a second current path from said output terminal to a power supply potential, which is different from said selected power supply potential, in response to the output signal of at least one of said internal circuits; said second semiconductor switch circuit being not turned ON simultaneously with said first semiconductor switch circuit under the steady state.

Claim 18

In a semiconductor integrated circuit device of the type wherein an input buffer circuit for inputting an external signal, an internal circuit for exhibiting a predetermined functional operation on the basis of the signal from said input buffer circuit and an output buffer circuit for outputting the output signal of said internal circuit to an external element are integrated on the same semiconductor substrate, the improvement wherein said output buffer circuit comprises: a selection signal generation circuit for generating a selection signal for selecting one of a plurality of power supply potentials; a power supply potential selection circuit for selecting one of said power supply potentials on the basis of said selection signal; a first semiconductor switch circuit for forming a first current path from said selected power supply potential to the output terminal to be connected to said external element in response to the output signal of at least one of said internal circuits; and a second semiconductor switch circuit for forming a second current path from said output terminal to a power supply potential, which is different from said selected power supply potential, in response to the output signal of at least one of said internal circuits; said second semiconductor switch circuit being not turned ON simultaneously with said first semiconductor switch circuit under the steady state.

Claim 19

A semiconductor integrated circuit device according to claim 16, wherein said input buffer circuit and/or said internal circuit operates between one of said power supply potentials and a power supply potential which is different from said selected power supply potential.

Claim 20

A semiconductor integrated circuit device according to claim 17, wherein said input buffer circuit and/or said internal circuit operates between the maximum value of a plurality of said power supply potentials and a power supply potential which is different from said selected power supply potential.

Claim 21

A semiconductor integrated circuit device according to claim 17, wherein said internal circuit performs a predetermined logical functional operation on the basis of the signal from said input buffer circuit.

Claim 22

A semiconductor integrated circuit device according to claim 16, wherein said selection signal generation circuit generates said selection signal on the basis of the signal applied thereto from outside of the semiconductor integrated circuit device.

Claim 23

A semiconductor integrated circuit device according to claim 20, wherein said selection signal generation circuit holds the signal applied thereto from outside for a predetermined period of time and generates said selection signal corresponding to the signal applied thereto from outside.

Claim 24

A semiconductor integrated circuit device according to claim 16, wherein said power supply potential selection circuit selects one of two power supply potentials.

Claim 25

A semiconductor integrated circuit device according to claim 22, wherein said power supply potential selection circuit consists of a third semiconductor switch circuit for selecting one of said two power supply potentials in response to said selection signal and a fourth semiconductor switch circuit for selecting the other of said two power supply potentials in response to the inversed signal of said selection signal.

Claim 26

A semiconductor integrated circuit device according to claim 22, wherein said power supply potential selection circuit consists of a third semiconductor switch circuit for selecting one of said two power supply potentials in response to said selection signal and a fourth semiconductor switch circuit for selecting the other of said two power supply potentials by operating complementarily with said third semiconductor switch circuit in response to said selection signal.

Claim 27

A semiconductor integrated circuit device according to claim 16, wherein said power supply potential selection circuit selects one of said power supply potentials from a predetermined junction of means for distributing voltage connected between a pair of power supply potentials.

Claim 28

A semiconductor integrated circuit device according to claim 16, wherein said first semiconductor switch circuit consists of at least one field effect transistor whose gate is connected to at least one of said input signals and whose source-drain current path forms said first current path.

Claim 29

A semiconductor integrated circuit device according to claim 16, wherein said at least one field effect transistor is a field effect transistor having a first conductivity type.

Claim 30

A semiconductor integrated circuit device according to claim 16, wherein said second semiconductor switch circuit consists of at least one field effect transistor whose gate is connected to at least one of said input signals and whose source-drain current path forms said second current path.

Claim 31

A semiconductor integrated circuit device according to claim 28, wherein said at least one field effect transistor is a field effect transistor having a second conductivity type.

Claim 32

A semiconductor integrated circuit device according to claim 16, wherein said first semiconductor switch circuit consists of at least one bipolar transistor whose collector-emitter current path forms said first current path; at least one field effect transistor whose gate is connected to at least one input signal and whose source-drain current path forms a current path from said selected power supply potential to the base of said at least one bipolar transistor; and a semiconductor device, connected to the base of said at least one bipolar transistor, and withdrawing the charge stored at said base.

Claim 33

A semiconductor integrated circuit device according to claim 30, wherein said at least one bipolar transistor is a bipolar transistor having the base of a first conductivity type and the collector and emitter of a second donductivity type, and said at least one field effect transistor is a field effect transistor of the first conductivity type.

Claim 34

A semiconductor integrated circuit device according to claim 16, wherein said second semiconductors switch circuit consists of at least one bipolar transistor whose collector-emitter current path forms said second current path; at least one field effect transistor whose gate is connected to at least one input signal and whose source-drain current path forms a current path from the output terminal to the base of said at least one bipolar transistor; and a semiconductor device connected, to the base of said at least one bipolar transistor, and withdrawing the charge stored at said base.

Claim 35

A semiconductor integrated circuit device according to claim 32, wherein said at least one bipolar transistor is a bipolar transistor having the base of a first conductivity type and the collector and emitter of a second conductivity type, and said at least one field effect transistor is a field effect transistor of the second conductivity type.

Claim 36

In a semiconductor integrated circuit device system including: a first semiconductor integrated circuit device including an input buffer circuit for inputting external signals, an internal circuit for conducting a predetermined functional operation on the basis of the signal from said input buffer circuit and an output buffer circuit for providing the output signal of said internal circuit to an external element, that are integrated on the same semiconductor substrate; and a second semiconductor integrated circuit device including an input circuit for inputting the signal from said output buffer circuit of said first semiconductor integrated circuit device, an internal circuit for conducting a predetermined functional operation on the basis of the signal from said input buffer circuit and an output buffer circuit for providing the output signal of said internal circuit to an external element that are integrated on the same semiconductor substrate; the improvement wherein said output buffer circuit of said first semiconductor integrated circuit device comprises: a selection signal generation circuit generating a selection signal for selecting one of a plurality of power supply potentials including the power supply potential corresponding to the operation power supply potential difference of said input buffer circuit of said second semiconductor integrated circuit device; a power supply potential selection circuit for selecting the operation power supply potential of said input buffer circuit of said second semiconductor integrated circuit device on the basis of said selection signal; a first semiconductor switch circuit for forming a first current path from said selected power supply potential to the output terminal connected to said input buffer circuit of said second semiconductor integrated circuit device in response to the output signal of at least one of said internal circuits; and a second semiconductor switch circuit for forming a second current path from said output terminal to a power supply potential, which is different from said selected power supply potential; said second semiconductor switch circuit being not turned ON simultaneously with said first semiconductor switch circuit under the steady state.

Claim 37

In a semiconductor integrated circuit device system including: a first semiconductor integrated circuit device including an input buffer circuit for inputting external signals, an internal circuit for conducting a predetermined functional operation on the basis of the signal from said input buffer circuit and an output buffer circuit for providing the output signal of said internal circuit to an external element, that are integrated on the same semiconductor substrate; and a second semiconductor integrated circuit device including an input circuit for inputting the signal from said output buffer circuit of said first semiconductor integrated circuit device, an internal circuit for conducting a predetermined functional operation on the basis of the signal from said input buffer circuit and an output buffer circuit for providing the output signal of said internal circuit to an external element that are integrated on the same semiconductor substrate; the improvement wherein said output buffer circuit of said first semiconductor integrated circuit device comprises: a selection signal generation circuit generating a selection signal for selecting one of a plurality of power supply potentials including the power supply potential corresponding to the operation power supply potential difference of said input buffer circuit of said second semiconductor integrated circuit device; a power supply potential selection circuit for selecting the operation power supply potential of said input buffer circuit of said second semiconductor integrated circuit device on the basis of said selection signal; a first semiconductor switch circuit for forming a first current path from said selected power supply potential to the output terminal connected to said input buffer circuit of said second semiconductor integrated circuit device in response to the output signal of at least one of said internal circuits; and a second semiconductor switch circuit for forming a second current path from said output terminal to a power supply potential, which is different from said selected power supply potential; said second semiconductor switch circuit being not turned ON simultaneously with said first semiconductor switch circuit under the steady state.

Claim 38

A semiconductor integrated circuit device system according to claim 34, wherein said first and second semiconductor integrated circuit devices are integrated on mutually different semiconductor substrates.

Claim 39

A semiconductor integrated circuit device system according to claim 34, wherein said first and second semiconductor integrated circuit devices are integrated on the same semiconductor substrate.

Claim 40

A semiconductor integrated circuit device system according to claim 34, wherein said input buffer circuit and/or said internal circuit operates between one of said power supply potentials and a power supply potential different from said selected power supply potential.

Claim 41

A semiconductor integrated circuit device system according to claim 37, wherein said input buffer circuit and/or said internal circuit operates between the maximum value of said power supply potentials and a power supply potential different from said selected power supply potential.

Claim 42

A semiconductor integrated circuit device system according to claim 34, wherein said internal circuit conducts a predetermined logical functional operation on the basis of the signal from said input buffer circuit.

Claim 43

A semiconductor integrated circuit device system according to claim 34, wherein said selection signal generation circuit generates said selection signal on the basis of the signal applied thereto from said second semiconductor integrated circuit device.

Claim 44

A semiconductor integrated circuit device system according to claim 40, wherein said selection signal generation circuit holds the signal applied thereto from said second semiconductor integrated circuit device for a predetermined period and generates said selection signal corresponding to the signal applied thereto from said second semiconductor integrated circuit device.

Claim 45

A semiconductor integrated circuit device system according to claim 34, wherein said power supply selection circuit selects one of two power supply potentials.

Claim 46

A semiconductor integrated circuit device system according to claim 42, wherein said power supply selection circuit consists of a third semiconductor switch circuit for selecting one of said two power supply potentials in response to said selection signal, and a fourth semiconductor switch circuit for selecting the other of said two power supply potentials in response to the inversed signal of said selection signal.

Claim 47

A semiconductor integrated circuit device system according to claim 42, wherein said power supply selection circuit consists of a third semiconductor switch circuit for selecting one of said two power supply potentials in response to said selection signal and a fourth semiconductor switch circuit for selecting the other of said two power supply potentials by operating complementarily to said third semiconductor switch circuit in response to said selection signal.

Claim 48

A semiconductor integrated circuit device system according to claim 34, wherein said power supply selection circuit selects one of said power supply potentials from a predetermined junction of voltage distribution means connected between a pair of power supply potentials.

Claim 49

A semiconductor integrated circuit device system according to claim 34, wherein said first semiconductor switch circuit consists of at least one field effect transistor whose gate is connected to at least one of said input signals and whose source-drain current path forms said first current path.

Claim 50

A semiconductor integrated circuit device system according to claim 46, wherein said at least one field effect transistor is a field effect transistor having a first conductivity type.

Claim 51

A semiconductor integrated circuit device system according to claim 34, wherein said second semiconductor switch consists of at least one field effect transistor whose gate is connected to at least one of said input signals and whose source-drain current path forms said second current path.

Claim 52

A semiconductor integrated circuit device system according to claim 48, wherein said at least one field effect transistor is a field effect transistor having a second conductivity type.

Claim 53

A semiconductor integrated circuit device system according to claim 34, wherein said first semiconductor switch circuit consists of at least one bipolar transistor whose collector-emitter current path forms said first current path; at least one field effect transistor whose gate is connected to at least one input signal and whose source-drain current path forms a current path from said selected power supply potential to the base of said at least one bipolar transistor; and a semiconductor device, connected to the base of said at least one bipolar transistor, and withdrawing the charge stored at said base.

Claim 54

A semiconductor integrated circuit device system according to claim 50, wherein said at least one bipolar transistor is a bipolar transistor having the base of a first conductivity type and the collector and emitter of a second conductivity type, and said at least one field effect transistor is a field effect transistor of the first conductivity type.

Claim 55

A semiconductor integrated circuit device system according to claim 34, wherein said second semiconductor switch circuit consists of at least one bipolar transistor whose collector-emitter current path forms said second current path; at least one field effect transistor whose gate is connected to at least one input signal and whose source-drain current path forms a current path from said output terminal to the base of said at least one bipolar transistor; and a semiconductor device connected to the base of said at least one bipolar transistor and withdrawing the charge stored at said base.

Claim 56

A semiconductor integrated circuit device system according to claim 52, wherein said at least one bipolar transistor is a bipolar transistor having the base of a first conductivity type and the collector and emitter of a second conductivity type, and said at least one field effect transistor is a field effect transistor of the second conductivity type.

Claim 57

A semiconductor integrated circuit device system according to claim 34, wherein at least one of said input buffer circuits of said second semiconductor integrated circuit device includes a first semiconductor switch circuit for forming a third current path from a predetermined power supply potential to the output terminal connected to said internal circuit in response to the output signal of said output buffer circuit of said first semiconductor integrated circuit device; and a second semiconductor switch circuit for forming a fourth current path from said output terminal to a power supply potential, which is different from said predetermined power supply potential, in response to the output signal of said output buffer circuit of said first semiconductor integrated circuit device.

Claim 58

A semiconductor integrated circuit device system according to claim 54, wherein said first semiconductor switch circuit of said second semiconductor integrated circuit device consists of at least one field effect transistor whose gate is connected to the output signal of said output buffer circuit of said first semiconductor integrated circuit device and whose source-drain current path forms said third current path.

Claim 59

A semiconductor integrated circuit device system according to claim 55, wherein said at least one field effect transistor is a field effect transistor of a first conductivity type.

Claim 60

A semiconductor integrated circuit device system according to claim 54, wherein said second semiconductor switch circuit of said second semiconductor integrated circuit device consists of at least one field effect transistor whose gate is connected to the output signal of said output buffer circuit of said first semiconductor integrated circuit device and whose source-drain current path forms said fourth current path.

Claim 61

A semiconductor integrated circuit device system according to claim 57, wherein said at least one field effect transistor is a field effect transistor of the second conductivity type.

Claim 62

A semiconductor integrated circuit device system according to claim 54, wherein said first semiconductor switch circuit of said second semiconductor integrated circuit device consists of at least one bipolar transistor whose collector-emitter current path forms said third current path; at least one field effect transistor whose gate is connected to the output signal of said output buffer circuit of said first semiconductor integrated circuit device and whose source-drain current path forms a current path from said selected power supply potential to the base of said at least one bipolar transistor; and a semiconductor device, connected to the base of said at least one bipolar transistor, withdrawing the charge at said base.

Claim 63

A semiconductor integrated circuit device system according to claim 59, wherein said at least one bipolar transistor is a bipolar transistor having the base of a first conductivity type and the collector and emitter of a second conductivity type, and said at least one field effect transistor is a field effect transistor of the first conductivity type.

Claim 64

A semiconductor integrated circuit device system according to claim 54, wherein said second semiconductor switch circuit of said second semiconductor integrated circuit device consists of at least one bipolar transistor whose collector-emitter current path forms said fourth current path; a field effect transistor whose gate is connected to the output signal of said output buffer circuit of said first semiconductor integrated circuit device and whose source-drain current path forms a current path from said output terminal to the base of said at least one bipolar transistor; and a semiconductor device, connected to the base of said at least one bipolar transistor, withdrawing the charge stored at said base.

Claim 65

A semiconductor integrated circuit device system according to claim 61, wherein said at least one bipolar transistor is a bipolar transistor having the base of a first conductivity type and the collector and emitter of a second conductivity type, and said at least one field effect transistor is a field effect transistor of the second conductivity type.

Claim 66

A semiconductor integrated circuit device system according to claim 16, wherein said selection signal generation circuit and/or said power supply potential selection circuit is disposed in the unit of said first and second semiconductor switch circuits.

Claim 67

A semiconductor integrated circuit device system according to claim 16, wherein said selection signal generation circuit and/or said power supply potential selection circuit is disposed in the unit of group consisting of plurality each of said first and second semiconductor switch circuits.

Claim 68

A semiconductor integrated circuit device system according to claim 34, wherein said second semiconductor integrated circuit device is memory LSI.

Claim 69

A semiconductor integrated circuit device characterized in that when counter-part power supply designation means designates a level such that the output circuit of a bi-directional input/output circuit to the common pin of which the output of an output circuit and the input of an input circuit in a first semiconductor integrated circuit device operating at a first power supply attains an output level suitable for the input of a second power supply system, the logical threshold values of the input circuits connected to the same pin are simultaneously controlled in such a manner as to be adaptive to the output level of LSI operating at a second power supply.

Claim 70

A semiconductor integrated circuit device characterized in that when counter-part power supply designation means designates a level such that the output circuit of a bi-directional input/output circuit to the common pin of which the output of an output circuit and the input of an input circuit in a first semiconductor integrated circuit device operating at a first power supply attains an output level suitable for the input of a second power supply system, the logical threshold values of the input circuits connected to the same pin are simultaneously controlled in such a manner as to be adaptive to the output level of LSI operating at a second power supply.