US4760282A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-speed, bootstrap driver circuit
Assignee: Semiconductor Components Industries LLC
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Filing: 1986-11-13
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Granted: 1988-07-26
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Expires: 2006-11-13
Abstract
Abstract A line driver circuit capable of operating at high speeds. The output transistor, an emitter connected to an output terminal, has a special feedback capacitor connected to its base. The feedback capacitor helps pull the output terminal high to increase the switching speed of the line driver circuit. Special current injection and removal techniques are used to speed the switching times of the PNP current supply transistors. The line driver circuit also has special circuitry to limit the output current from exceeding certain limits and for keeping the line driver circuit from overheating.
Inventors
- 👤 James R. Kuo
- 👤 Brian R. Carey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:55
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/02; H03K19/00; H03K19/003; H03K19/00307; H03K19/01; H03K19/013; H03K19/0133; H03K19/02; H03K19/08; H03K19/082; H03K19/0823; H03K19/0826
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
191 words
A circuit for driving digital signals from a signal source through an output terminal onto a line, said circuit comprising: an output transistor having an emitter terminal connected to said output terminal, a base terminal connected to a first current source, and a collector terminal coupled to a first voltage supply source; a second transistor having an emitter terminal connected to said base terminal of said output transistor, a base terminal connected to a second current source, and a collector terminal coupled to said first voltage supply source; switching means connected to said output terminal, said base terminal of said output transistor and said base terminal of said second transistor, said switching mean coupling and uncoupling said output terminal, and said base terminals of said output and second transistors to ground, responsive to a data signal from said signal source; and capacitive means connected to said base terminal of said output transistor and to said base terminal of said second transistor through a first impedance means, said capacitive means raising the voltage to said base terminal of said second transistor to decrease the switch-on times of said output and second transistors.
Claim 2
Dependent Claim
191 words
A circuit for driving digital signals from a signal source through an output terminal onto a line, said circuit comprising: an output transistor having an emitter terminal connected to said output terminal, a base terminal connected to a first current source, and a collector terminal coupled to a first voltage supply source; a second transistor having an emitter terminal connected to said base terminal of said output transistor, a base terminal connected to a second current source, and a collector terminal coupled to said first voltage supply source; switching means connected to said output terminal, said base terminal of said output transistor and said base terminal of said second transistor, said switching mean coupling and uncoupling said output terminal, and said base terminals of said output and second transistors to ground, responsive to a data signal from said signal source; and capacitive means connected to said base terminal of said output transistor and to said base terminal of said second transistor through a first impedance means, said capacitive means raising the voltage to said base terminal of said second transistor to decrease the switch-on times of said output and second transistors.
Claim 3
Dependent Claim
22 words
The driving circuit as in claim 1 further comprising a second impedance means, said second impedance means and said second current source.
Claim 4
Dependent Claim
52 words
The driving circuit as in claim 1 further comprising a third transistor, said third transistor having an emitter terminal connected to a node between said first and second impedance means, a base terminal connected to said second current source, and a collector terminal connected to a collector terminal of said second transistor.
Claim 5
Dependent Claim
26 words
The driving circuit as in claim 3 wherein the impedance of said first impedance means is much smaller than the impedance of said second impedance means.
Claim 6
Dependent Claim
48 words
The driving circuit as in claim 3 wherein said switching means comprises a fourth transistor having an emitter terminal coupled to ground, a collector terminal connected to said base terminal of said second transistor through a first rectifying means, and a base terminal connected to said signal source.
Claim 7
Dependent Claim
53 words
The driving circuit as in claim 5 wherein said switching means further comprises a fifth transistor having an emitter terminal coupled to ground, a collector terminal connected to said base terminal of said second transistor through a second rectifying means and third impedance means, and a base terminal connected to said signal source.
Claim 8
Dependent Claim
49 words
The driving circuit as in claim 6 wherein said switching means further comprises a sixth transistor having an emitter terminal coupled to ground, a collector terminal connected to said output terminal through a third rectifying means, and a base terminal connected to said emitter terminal of said fourth transistor.
Claim 9
Dependent Claim
28 words
The driving circuit as in claim 1 wherein said output and second transistors are PNP transistors, each having its base and collector regions connected by a Schottky diode.
Claim 10
Dependent Claim
194 words
A digital logic circuit comprising: a first transistor having an emitter terminal connected to an output terminal, a base terminal connected to a first current source, and a collector terminal coupled to a first voltage supply source; a second transistor having an emitter terminal connected to said base terminal of said first switching transistor, a base terminal connected to a second current source, and a collector terminal coupled to said first voltage supply source; switching means connected to said output terminal, said base terminal of said first transistor and said base terminal of said second transistor, said switching means coupling and uncoupling said emitter and base terminals of said first transistor and said base terminal of said second transistor to a second voltage supply reference responsive to a digital logic signal from a signal source; and capacitive means connected to said base terminal of said output transistor and to said base terminal of said second transistor through a first impedance means, said capacitive means raising the voltage to said base terminals of said first and second transistors as said first transistor turns on to decrease the switch-on times of said first and second transistors.
Claim 11
Dependent Claim
194 words
A digital logic circuit comprising: a first transistor having an emitter terminal connected to an output terminal, a base terminal connected to a first current source, and a collector terminal coupled to a first voltage supply source; a second transistor having an emitter terminal connected to said base terminal of said first switching transistor, a base terminal connected to a second current source, and a collector terminal coupled to said first voltage supply source; switching means connected to said output terminal, said base terminal of said first transistor and said base terminal of said second transistor, said switching means coupling and uncoupling said emitter and base terminals of said first transistor and said base terminal of said second transistor to a second voltage supply reference responsive to a digital logic signal from a signal source; and capacitive means connected to said base terminal of said output transistor and to said base terminal of said second transistor through a first impedance means, said capacitive means raising the voltage to said base terminals of said first and second transistors as said first transistor turns on to decrease the switch-on times of said first and second transistors.
Claim 12
Dependent Claim
27 words
The circuit as in claim 9 further comprising a second impedance means, said second impedance means connected between said first impedance means and said second current source.
Claim 13
Dependent Claim
51 words
The circuit as in claim 10 further comprising a third transistor, said third transistor having an emitter terminal connected to a node between said first and second impedance means, a base terminal connected to said second current source, and a collector terminal connected to said collector terminal of said second transistor.
Claim 14
Dependent Claim
25 words
The circuit as in claim 11 wherein the impedance of said first impedance means is much smaller than the impedance of said second impedance means.
Claim 15
Dependent Claim
47 words
The circuit as in claim 12 wherein said switching means comprises a fourth transistor having an emitter terminal coupled to ground, a collector terminal connected to said base terminal of said second transistor through a first rectifying means, and a base terminal connected to said signal source.
Claim 16
Dependent Claim
56 words
The circuit as in claim 13 wherein said switching means further comprises a fifth transistor having an emitter terminal coupled to said second voltage supply source, a collector terminal connected to said base terminal of said second transistor through a second rectifying means and third impedance means, and a base terminal connected to said signal source.
Claim 17
Dependent Claim
56 words
The circuit as in claim 14 wherein said switching means further comprises a sixth transistor having an emitter terminal coupled to said second voltage supply source, a collector terminal connected to said emitter terminal of said first transistor through a third rectifying means, and a base terminal connected to said emitter terminal of said fourth transistor.
Claim 18
Dependent Claim
28 words
The circuit as in claim 10 wherein said first, second and third transistors are PNP transistors, each having its base and collector regions connected by a Schottky diode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-07-26 | 1992-01-25 | 1992-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-07-26 | 1996-01-25 | 1996-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-07-26 | 2000-01-25 | 2000-07-26 | $7700.00 | Window Closed / Lapsed |