Voltage variable integrated circuit capacitor and bootstrap driver circuit

Claim 2

A voltage variable integrated capacitor comprising: three p-n junction diodes serially connected between a reference potential and a voltage node, the center one of said p-n junction diodes being oppositely poled with respect to the remaining two of said p-n junction diodes; input means for coupling an input signal to a point between said p-n junction diode nearest said voltage node and said center p-n junction diode; and biasing means coupled to said diodes for maintaining all three of said diodes in a reverse biased condition, said p-n junction diode nearest said voltage node providing a capacitively coupled output signal to said voltage node in response to an input signal.

Claim 3

The capacitor of claim 1 wherein said three pn junction diodes are formed on a single integrated circuit chip and the diode nearest said reference potential comprises an isolation junction and said biasing means comprises a fixed potential.

Claim 4

The capacitor of claim 2 wherein said p-n junction diode nearest said voltage node comprises an emitter-like region and a base-like region of a bipolar transistor-like structure.

Claim 5

In an integrated circuit, the combination comprising: a semiconductor substrate of a first conductivity type; a first region of a second conductivity type formed on a surface of said substrate, said first region being bounded by a first p-n junction; a second region of said first conductivity type formed in said first region, said second region being bounded by a second p-n junction; a third region of said second conductivity type formed in said second region, said third region being bounded by a third p-n junction; first terminal means connected to said second region for receiving an input voltage signal; second terminal means connected to said third region for providing a capacitively coupled output signal; and biasing means for maintaining the p-n junctions formed between said substrate and said first region and between said first region and said second region in a reverse biased condition to provide electrical isolation between said second region and said substrate and to provide capacitive coupling of a portion of said input signal from said first terminal means to said second terminal means.

Claim 6

In an integrated circuit, the combination comprising: a semiconductor substrate of a first conductivity type; a first region of a second conductivity type formed on a surface of said substrate, said first region being bounded by a first p-n junction; a second region of said first conductivity type formed in said first region, said second region being bounded by a second p-n junction; a third region of said second conductivity type formed in said second region, said third region being bounded by a third p-n junction; first terminal means connected to said second region for receiving an input voltage signal; second terminal means connected to said third region for providing a capacitively coupled output signal; and biasing means for maintaining the p-n junctions formed between said substrate and said first region and between said first region and said second region in a reverse biased condition to provide electrical isolation between said second region and said substrate and to provide capacitive coupling of a portion of said input signal from said first terminal means to said second terminal means.

Claim 7

The integrated circuit of claim 4 wherein said biasing means comprises means to apply a supply potential to said first region and a reference potential to said substrate.

Claim 8

An integrated bipolar bootstrap circuit formed on a semiconductor substrate comprising: at least one bipolar amplifier stage having an input and an output; and feedback means comprising a resistor and a capacitor, said capacitor being formed in a p-n junction-isolated region of said substrate and including a first capacitor terminal directly coupled to said output and being capacitively coupled to said p-n junction-isolated region through a reverse biased first p-n junction, said capacitor also including a second capacitor terminal connected to said resistor and being electrically coupled to said first capacitor terminal through a reverse biased second p-n junction.

Claim 9

An integrated bipolar bootstrap circuit formed on a semiconductor substrate comprising: at least one bipolar amplifier stage having an input and an output; and feedback means comprising a resistor and a capacitor, said capacitor being formed in a p-n junction-isolated region of said substrate and including a first capacitor terminal directly coupled to said output and being capacitively coupled to said p-n junction-isolated region through a reverse biased first p-n junction, said capacitor also including a second capacitor terminal connected to said resistor and being electrically coupled to said first capacitor terminal through a reverse biased second p-n junction.

Claim 10

The integrated circuit of claim 6 wherein said amplifier stage comprises an emitter follower circuit.

Claim 11

The integrated circuit of claim 7 wherein said second capacitor terminal is coupled to a common current source for providing current to charge said second terminal and to provide current to said amplifier stage.

Claim 12

The integrated circuit of claim 8 wherein said capacitor comprises a bipolar transistor-like structure including a plurality of emitter-like regions forming said reverse biased second p-n junction with a base-like region, and said base-like region and a collector-like region forming said reverse biased first p-n junction.

Claim 13

In a p-n junction isolated bipolar drive integrated circuit comprising: a semiconductor substrate; an amplifier driver stage having an input and an output and being formed in said substrate; a first p-n junction capacitor having two terminals formed in a p-n junction isolated region on said substrate, said first capacitor being coupled between the input and the output of said amplifier drive stage, the terminals of said first capacitor being electrically isolated from said substrate by at least one reverse biased p-n junction, and a second p-n junction capacitor having two terminals formed in said p-n junction isolated region on said substrate, said second capacitor being coupled between the output of said amplifier drive stage and a fixed potential source, the terminals of said second capacitor being electrically isolated from said substrate by said at least one reverse biased p-n junction.

Claim 14

In a p-n junction isolated bipolar drive integrated circuit comprising: a semiconductor substrate; an amplifier driver stage having an input and an output and being formed in said substrate; a first p-n junction capacitor having two terminals formed in a p-n junction isolated region on said substrate, said first capacitor being coupled between the input and the output of said amplifier drive stage, the terminals of said first capacitor being electrically isolated from said substrate by at least one reverse biased p-n junction, and a second p-n junction capacitor having two terminals formed in said p-n junction isolated region on said substrate, said second capacitor being coupled between the output of said amplifier drive stage and a fixed potential source, the terminals of said second capacitor being electrically isolated from said substrate by said at least one reverse biased p-n junction.