US4861731A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating a lateral dual gate thyristor
Assignee: Motors Liquidation Co
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Filing: 1988-02-02
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Granted: 1989-08-29
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Expires: 2008-02-02
Abstract
Abstract A semiconductor power device with bipolar regenerative switching characteristics provides insulated gate structures for controlling device turn-on and turn-off. Rapid turn-off is achieved in part by a lateral field effect pinch resistance and a vertical field effect pinch resistance produced by an electrically floating structure. The device is electrically isolated by layer of dielectric which allows it to be easily integrated with other circuit elements. The device can be controlled by low current and low positive voltages which provides for simpler interfacing and better electrical compatibility with other circuits in an automotive system. A method of manufactuing this device is also provided.
Inventors
- 👤 Jayant K. Bhagat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:16
CPC Classifications
H; H10; H10D; H10D18/00; H10D18/251
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
254 words
A method for forming a semiconductor power device comprising the steps of: (A) forming an electrically isolated region of semiconductor material in a substrate, said isolated region having a first conductivity type; (B) forming a buried layer of highly conductive semiconductor material is said electrically isolated region; (C) forming a highly conductive ring in said isolated region; (D) introducing dopant impurities into a region within said ring to form an island having second conductivity type; (E) forming strips of highly conductive semiconductor material at the surface of said electrically isolated region, said strips having said first conductivity type and electrically linking said ring and said highly conductive buried layer; (F) forming a heavily doped cathode region within said island, by said cathode region having said first conductivity type; (G) forming an anode region within said isolated region; (H) doping a portion of said isolated region between said ring and said anode to form a channel having said second conductivity type; (I) forming a drain region within said channel at the surface of said isolated region; (J) forming a layer of dielectric over the surface of said isolated region; (K) depositing a layer of electrode material over said layer of said dielectric material; and (L) etching said electrode layer and said dielectric material to define contact windows respectively above said cathode, ring, drain and anode to define a first insulated gate electrode registering with a portion of said island and to define a second insulated gate electrode registering with a portion of said isolated region.
Claim 2
Independent Claim
254 words
A method for forming a semiconductor power device comprising the steps of: (A) forming an electrically isolated region of semiconductor material in a substrate, said isolated region having a first conductivity type; (B) forming a buried layer of highly conductive semiconductor material is said electrically isolated region; (C) forming a highly conductive ring in said isolated region; (D) introducing dopant impurities into a region within said ring to form an island having second conductivity type; (E) forming strips of highly conductive semiconductor material at the surface of said electrically isolated region, said strips having said first conductivity type and electrically linking said ring and said highly conductive buried layer; (F) forming a heavily doped cathode region within said island, by said cathode region having said first conductivity type; (G) forming an anode region within said isolated region; (H) doping a portion of said isolated region between said ring and said anode to form a channel having said second conductivity type; (I) forming a drain region within said channel at the surface of said isolated region; (J) forming a layer of dielectric over the surface of said isolated region; (K) depositing a layer of electrode material over said layer of said dielectric material; and (L) etching said electrode layer and said dielectric material to define contact windows respectively above said cathode, ring, drain and anode to define a first insulated gate electrode registering with a portion of said island and to define a second insulated gate electrode registering with a portion of said isolated region.
Claim 3
Dependent Claim
53 words
The method of forming a semiconductor power device recited in claim 1, including the steps of forming a layer of electrically insulative material on said dielectric layer and said first and second insulated gate electrodes, opening contact windows in said electrically insulative material, and depositing a metalization layer on said electrically insulative layer.
Claim 4
Dependent Claim
38 words
The method of forming a semiconductor power device recited in claim 2, including the step of etching said metalization layer to form separate metal contacts for said cathode, anode, first insulated gate electrode and second insulated gate electrode.
Claim 5
Dependent Claim
28 words
The method of forming a semiconductor power device recited in claim 3, including the step of etching and metalization to form a separate metal contact for said drain.
Claim 6
Dependent Claim
23 words
The method of forming a semiconductor power device recited in claim 1, including the step of electrically shorting said cathode to said island.
Claim 7
Dependent Claim
26 words
The method of forming a semiconductor power device recited in claim 1, including the step of electrically shorting said anode to said electrically isolated semiconductor region.
Claim 8
Dependent Claim
135 words
The method of forming a semiconductor power device recited in claim 1, wherein said steps (A) and (B) are each performed by: etching at least two grooves in the surface of a semiconductor wafer to form a cell; forming a highly conductive layer of semiconductor material over the surface of said cell and over the sidewalls of said grooves; forming a layer of buried insulative material on said highly conductive layer; depositing a film of polysilicon over said grooved wafer surface,thereby filling said grooves with polysilicon; removing semiconductor material from the side of said wafer opposite the side of said wafer which includes said grooved surface to a depth such that the apices of said grooves are removed and said electrically isolated semiconductor region is electrically insulative from said polysilicon by said buried insulative material.
Claim 9
Dependent Claim
45 words
The method of forming a semiconductor power device recited in claim 7, wherein said buried insulative material is a layer of silicon dioxide formed by depositing a thin layer of conductive buried layer and oxidizing said thin polysilicon layer to form said buried insulative material.
References Cited (Backward Citations)
US3320485A
Cited
US3427709A
Cited
SU228793A1
Cited
US3579391A
Cited
US3585463A
Cited
US3623218A
Cited
US3722079A
Cited
US3891866A
Cited
JPS5267580A
Cited
DE2807181A1
Cited
US4287526A
Cited
US4199774A
Cited
US4608590A
Cited
JPS55115340A
Cited
US4242697A
Cited
JPS5795633A
Cited
US4458408A
Cited
US4742380A
Cited
FR2524711A1
Cited
US4654691A
Cited
US4605872A
Cited
JPS59110132A
Cited
US4604638A
Cited
US4611235A
Cited
US4612562A
Cited
US4593458A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-28 | 1993-02-27 | 1993-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-28 | 1997-02-27 | 1997-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-28 | 2001-02-27 | 2001-08-29 | $7700.00 | Window Closed / Lapsed |