Fabrication of integrated circuit with complementary, dielectrically-isolated, high voltage semiconductor devices

Claim 1

A method of fabricating an integrated circuit including first and second, dielectrically-isolated complementary, high voltage semiconductor devices, the first semiconductor device including a first voltage-supporting region of one conductivity type and the second device including a second voltage-supporting region of opposite conductivity type, said first and second voltage-supporting regions being of the lateral-current conduction type, the method comprising the steps of: (a) providing a semiconductor wafer including partially-formed first and second insulating tubs in which said first and second semiconductor devices are to be respectively formed; (b) epitaxially growing in said first and second insulating tubs, respectively, first and second semiconductor layers, respectively, said epitaxially-grown layers being doped to the one conductivity type with a doping concentration below 20 percent of the final doping concentration of said first device voltage-supporting region; (c) introducing the opposite conductivity type dopant into said second layer to complete the doping of said second voltage-supporting region, said dopant being limited in amount such that said second voltage-supporting region is entirely depletable at a rated blocking voltage of the second semiconductor device; (d) introducing the one conductivity type dopant into said first layer to complete the doping of said first voltage-supporting region, said dopant being limited to such an extent that the first voltage-supporting region is entirely depletable at a rated blocking voltage of said first semiconductor device; (e) forming respective main current semiconductor regions in said first and second layers; and (g) forming main current electrodes on said main current semiconductor regions.

Claim 2

A method of fabricating an integrated circuit including first and second, dielectrically-isolated complementary, high voltage semiconductor devices, the first semiconductor device including a first voltage-supporting region of one conductivity type and the second device including a second voltage-supporting region of opposite conductivity type, said first and second voltage-supporting regions being of the lateral-current conduction type, the method comprising the steps of: (a) providing a semiconductor wafer including partially-formed first and second insulating tubs in which said first and second semiconductor devices are to be respectively formed; (b) epitaxially growing in said first and second insulating tubs, respectively, first and second semiconductor layers, respectively, said epitaxially-grown layers being doped to the one conductivity type with a doping concentration below 20 percent of the final doping concentration of said first device voltage-supporting region; (c) introducing the opposite conductivity type dopant into said second layer to complete the doping of said second voltage-supporting region, said dopant being limited in amount such that said second voltage-supporting region is entirely depletable at a rated blocking voltage of the second semiconductor device; (d) introducing the one conductivity type dopant into said first layer to complete the doping of said first voltage-supporting region, said dopant being limited to such an extent that the first voltage-supporting region is entirely depletable at a rated blocking voltage of said first semiconductor device; (e) forming respective main current semiconductor regions in said first and second layers; and (g) forming main current electrodes on said main current semiconductor regions.