Method for the fabrication of dielectric isolated junction field effect transistor and PNP transistor

Claim 1

The method of fabricating a dielectrically isolated junction field effect transistor and a PNP transistor comprising the steps of: diffusing impurities of a first semiconductor type into the first surface of a semiconductor substrate to form a first and second region; diffusing impurities of said first semiconductor type into said first surface of said semiconductor substrate and in contact with said first region to form a shallow pocket, grooving said first surface of said semiconductor substrate and coating said grooves with an insulator to dielectrically isolate said first and second regions from each other; depositing a second semiconductor material on the insulator on said first surface of said semiconductor substrate; selectively forming an epitaxial layer of second semiconductor type on said second surface of said first semiconductor material in contact with said second region; diffusing impurities of said second semiconductor type into said epitaxial layer to form a third and fourth region; diffusing impurities of a said first semiconductor type into said epitaxial layer to form a fifth region between said third and fourth region and separated from both; diffusing impurities of said second semiconductor type into another portion of the second surface of said first semiconductor type adjacent to but separated from said diffused impurities of said first semiconductor type to form the base of a transistor; introducing impurities into said first region to form the collector of a transistor; diffusing impurities of a third semiconductor type into said base of said transistor to form the emitter of said transistor; said epitaxial layer, said third, fourth and fifth regions forming the channel, source, drain and gate respectively of a dielectrically isolated junction field effect transistor.

Claim 2

The method of fabricating a dielectrically isolated junction field effect transistor and a PNP transistor comprising the steps of: diffusing impurities of a first semiconductor type into the first surface of a semiconductor substrate to form a first and second region; diffusing impurities of said first semiconductor type into said first surface of said semiconductor substrate and in contact with said first region to form a shallow pocket, grooving said first surface of said semiconductor substrate and coating said grooves with an insulator to dielectrically isolate said first and second regions from each other; depositing a second semiconductor material on the insulator on said first surface of said semiconductor substrate; selectively forming an epitaxial layer of second semiconductor type on said second surface of said first semiconductor material in contact with said second region; diffusing impurities of said second semiconductor type into said epitaxial layer to form a third and fourth region; diffusing impurities of a said first semiconductor type into said epitaxial layer to form a fifth region between said third and fourth region and separated from both; diffusing impurities of said second semiconductor type into another portion of the second surface of said first semiconductor type adjacent to but separated from said diffused impurities of said first semiconductor type to form the base of a transistor; introducing impurities into said first region to form the collector of a transistor; diffusing impurities of a third semiconductor type into said base of said transistor to form the emitter of said transistor; said epitaxial layer, said third, fourth and fifth regions forming the channel, source, drain and gate respectively of a dielectrically isolated junction field effect transistor.