Controlled anisotropic etching process for fabricating dielectrically isolated field effect transistor

Claim 1

The method as recited in claim 1 wherein said body has a (100) crystallographic structure.

Claim 6

A method for regulating and controlling the depth of a tub-like semiconductive region which extends down into a substrate material comprising the steps of: masking the planar surface of a body of semiconductive material with the mask having apertures of a predetermined size therethrough, said apertures being located outside and spaced from an area on said planar surface which is to serve as the bottom surface of said tub-like structure, etching said body of semiconductive material of a cystallographic orientation which is preferentially etched in a direction perpendicular to said planar surface by an anisotropic etching solution which preferentially etches crystallographic planes parallel to said planar surface through said apeRtures such that said semi-conductive material is etched to a predetermined depth beneath said planar surface so as to form corresponding apertures therein the bottom surface of each of said apertures in said body being planar and forming a first mesa parallel to said planar surface having an area of a size that is significant with respect to the area of the bottom surface of said tub-like structure, masking over the area on said planar surface which is to serve as the bottom surface of said tub-like structure with a mask impervious to said anisotropic etching solution, etching the exposed surface of said body with said anisotropic etching solution to a depth equal to the desired tub depth, said depth being determined by measurements of the extent of the exposed surface after etching, the mask dimensions of said last mentioned mask and characteristics of said crystallographic structure and its response to said anisotropic etching solution, the most extensive surface formed by said second etching step forming a second mesa, having an area of a size that is significant with respect to the area of the bottom surface of said tub-like structure, removing said last mentioned mask from over top of said area, applying a uniform dielectric layer over top of said body, forming said substrate material on top of said dielectric layer, lapping said semiconductive material with a coarse abrasive material from a surface of said body opposite said etched surface until the dielectric material covering said first mesa is at least partially exposed, continuing lapping said body of said semiconductor material and said dielectric material with the coarse abrasive material until all the dielectric material covering said first mesa is exposed, and lapping said semiconductive material from said exposed dielectric material with a fine abrasive material until said mesa is at least partially exposed as indicated by the removal of at least part of the dielectric material covering said second mesa, and continuing lapping said body of said semiconductor material and said dielectric material until all the dielectric material is removed whereby the depth of the tub-like structure thus produced is equal to the depth of said second etching step and whereby the accuracy of the depth of the tub-like structure is increased by the use of the two mesas as visual cues or indicators in the lapping steps.