US3876480A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing high speed, isolated integrated circuit
Assignee: Motorola Solutions Inc
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Filing: 1973-09-13
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Granted: 1975-04-08
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Expires: 1993-09-13
Abstract
Abstract Extremely high speed, low parasitic capacitance, isolated integrated circuits utilizing very thin epitaxial monocrystalline material in which active devices are formed, is taught. The very thin epitaxial layer is grown over an area that has been diffused with a selected impurity within a monocrystalline substrate. This is accomplished by diffusing from one side of the substrate and then growing the epitaxial layer on the other side, after sufficient material has been removed from the other side to reach the diffused region. The impurity concentration at the surface of the substrate into which the impurities were introduced is much higher than on the other side where the epitaxial layer is grown, making it possible to obtain a very thin epitaxial layer without faults. The very thin epitaxial layer makes unique integrated circuit configuration possible.
Inventors
- 👤 Uryon S Davidsohn
- 👤 Administrator By Amil J Ajamie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 14:09
CPC Classifications
H; H10; H10D; H10D99/00; H10P; H10P95/00; H10W; H10W10/00; H10W10/01; H10W10/021; H10W10/20; Y; Y10; Y10S; Y10S148/00; Y10S148/007; Y10S148/037; Y10S148/051; Y10S148/085; Y10S148/097; Y10S438/00; Y10S438/928
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
108 words
THE PROCESS OF MANUFACTURING A HIGH SPEED INTEGRATED CIRCUIT STRUCTURE COMPRISING THE STEPS OF: A. DIFFUSING FIRST SELECTED IMPURIITY TO FORM AT LEAST ONE BURIED LAYER REGION FORM ONE SIDE OF A SEMICONDUCTIVE MONOCRYSTALLINE SUBSTRATE; B. FORMING AN OXIDE LAYER ON THE ONE SIDE OF THE SUBSTRATE; C. FORMING A SUPPORT MEMBER OVER THE OXIDE LAYER; D. REMOVING MATERIAL FROM OTHER SIDE OF THE SUBSTRATE; UNTIL THE BURIED LAYER REGION IS REACHED OR NEARLY REACHED; AND E. GROWING AN EPITAXIAL LAYER ON THE OTHER SIDE OF THE SUBSTRATE OVER THE BURIED LAYER REGION TO PROVIDE AT LEAST ONE DISCRETE REGION OF A MONOCRYSTALLINE LAYER FOR DESIRED FURTHER DIFFUSIONS.
Claim 2
Dependent Claim
108 words
THE PROCESS OF MANUFACTURING A HIGH SPEED INTEGRATED CIRCUIT STRUCTURE COMPRISING THE STEPS OF: A. DIFFUSING FIRST SELECTED IMPURIITY TO FORM AT LEAST ONE BURIED LAYER REGION FORM ONE SIDE OF A SEMICONDUCTIVE MONOCRYSTALLINE SUBSTRATE; B. FORMING AN OXIDE LAYER ON THE ONE SIDE OF THE SUBSTRATE; C. FORMING A SUPPORT MEMBER OVER THE OXIDE LAYER; D. REMOVING MATERIAL FROM OTHER SIDE OF THE SUBSTRATE; UNTIL THE BURIED LAYER REGION IS REACHED OR NEARLY REACHED; AND E. GROWING AN EPITAXIAL LAYER ON THE OTHER SIDE OF THE SUBSTRATE OVER THE BURIED LAYER REGION TO PROVIDE AT LEAST ONE DISCRETE REGION OF A MONOCRYSTALLINE LAYER FOR DESIRED FURTHER DIFFUSIONS.
Claim 3
Dependent Claim
13 words
The process of claim 1 wherein the epitaxial layer is of N conductivity
Claim 4
Dependent Claim
46 words
The process of claim 1 wherein the substrate is comprised of a first conductivity type silicon, the buried layer region is comprised of a second conductivity type and the epitaxial layer is comprised of a second conductivity type silicon having an impurity concentration less than that
Claim 5
Dependent Claim
20 words
The process of claim 3 further comprising the step of: k. etching through the epitaxial layer to provide partial dielectric
Claim 6
Dependent Claim
34 words
The process of claim 3 further comprising the step of: i. etching through the epitaxial layer and the substrate to the oxide to provide full bottom dielectric isolation and air gap isolation in the
Claim 7
Dependent Claim
31 words
The process of claim 1, after the step of diffusing a selected impurity, further comprising the step of: m. diffusing a second selected impurity to form a diffused region from the
Claim 8
Dependent Claim
70 words
The process of claim 6 wherein the substrate is comprised of a first conductivity type silicon, the buried layer region is comprised of a second conductivity type, the diffused region is formed of the first conductivity type wherein the impurity concentration is heavier than that of the substrate to form a first section of a diffusion isolation barrier, and the epitaxial layer is of a second conductivity type silicon wherein
Claim 9
Dependent Claim
133 words
The process of manufacturing a high speed integrated circuit structure comprising the steps of: a. diffusing a selected impurity uniformly into one side of a semiconductive monocrystalline substrate to form a uniform diffusion; b. etching channels into the one side of the substrate to define at least one discrete area; c. forming an oxide layer over the one side of the substrate and in the channels; d. forming a support member over the oxide layer; e. removing material from the other side of the substrate until a uniform diffusion is reached or nearly reached; f. etching grooves through the other side of the substrate to the oxide layer in the channels, leaving at least one discrete section of the substrate; and g. growing an epitaxial layer over the remaining section of the substrate
Claim 10
Dependent Claim
133 words
The process of manufacturing a high speed integrated circuit structure comprising the steps of: a. diffusing a selected impurity uniformly into one side of a semiconductive monocrystalline substrate to form a uniform diffusion; b. etching channels into the one side of the substrate to define at least one discrete area; c. forming an oxide layer over the one side of the substrate and in the channels; d. forming a support member over the oxide layer; e. removing material from the other side of the substrate until a uniform diffusion is reached or nearly reached; f. etching grooves through the other side of the substrate to the oxide layer in the channels, leaving at least one discrete section of the substrate; and g. growing an epitaxial layer over the remaining section of the substrate
Claim 11
Dependent Claim
142 words
The process of manufacturing a high speed integrated circuit structure comprising the steps of: a. diffusing a selective impurity uniformly into one side of a semiconductive monocrystalline substrate to form a uniform diffusion; b. etching channels into the one side of the substrate to define at least one discrete area; c. forming an oxide layer over the one side of the substrate and in the channels; d. forming a support member over the oxide layer; e. removing material from the other side of the substrate until the uniform diffusion is reached or nearly reached; f. growing an epitaxial layer over the other side of the substrate to provide a monocrystalline layer for desired further diffusions; and g. etching grooves through the epitaxial layer and the other side of the substrate to the oxide layer in the channels thereby defining at least one
Claim 12
Dependent Claim
142 words
The process of manufacturing a high speed integrated circuit structure comprising the steps of: a. diffusing a selective impurity uniformly into one side of a semiconductive monocrystalline substrate to form a uniform diffusion; b. etching channels into the one side of the substrate to define at least one discrete area; c. forming an oxide layer over the one side of the substrate and in the channels; d. forming a support member over the oxide layer; e. removing material from the other side of the substrate until the uniform diffusion is reached or nearly reached; f. growing an epitaxial layer over the other side of the substrate to provide a monocrystalline layer for desired further diffusions; and g. etching grooves through the epitaxial layer and the other side of the substrate to the oxide layer in the channels thereby defining at least one
Claim 13
Dependent Claim
54 words
The process of claim 8 wherein the substrate is comprised of a first conductivity type silicon, the uniform diffusion is comprised of a second conductivity type to form a buried layer and the epitaxial layer is comprised of a second conductivity type silicon having a lesser impurity concentration than that of the uniform diffusion.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-04-07 | 1978-10-07 | 1979-04-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-04-07 | 1982-10-07 | 1983-04-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-04-07 | 1986-10-07 | 1987-04-08 | $7700.00 | Window Closed / Lapsed |