← Back to Patent Explorer
US4458408A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for making a light-activated line-operable zero-crossing switch

Assignee: Semiconductor Components Industries LLC
•
Filing: 1983-04-11
•
Granted: 1984-07-10
•
Expires: 2003-04-11
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A monolithic light-activated line-operable zero-crossing switch and method of making the same. The device comprises anti-parallel thyristors, each of whose gates is shunted by a field effect transistor. Each device may also be shunted by a resistor to reduce the overall sensitivity. The method of making the device contemplates surrounding the field effect transistor gate electrode and an internal shunt electrode by the primary metallization which forms the contact to the two main terminals of the device.

Inventors

  • 👤 Paul G. Alonas
  • 👤 David M. Gilbert
  • 👤 II Vernon P. O'Neil

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 11:28
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/78; H03K17/79; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/403

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 86 words
In a method for forming a monolithic light-operated thyristor trigger switch composed of vertical transistors and lateral transistors, each having an emitter, base, and collector region, the improvement comprising: disposing the emitter region of a first of the lateral transistors so as to lie between the emitter and collector regions of a second of the lateral transistors; and disposing the emitter region of a second of the lateral transistors so as to lie between the emitter and collector regions of the first of the lateral transistors.
Claim 2
Dependent Claim 86 words
In a method for forming a monolithic light-operated thyristor trigger switch composed of vertical transistors and lateral transistors, each having an emitter, base, and collector region, the improvement comprising: disposing the emitter region of a first of the lateral transistors so as to lie between the emitter and collector regions of a second of the lateral transistors; and disposing the emitter region of a second of the lateral transistors so as to lie between the emitter and collector regions of the first of the lateral transistors.
Claim 3
Dependent Claim 24 words
The method of claim 1 further comprising locating the emitter regions of the first and second lateral transistors in a substantially parallel separated relationship.
Claim 4
Dependent Claim 27 words
The method of claim 2 further comprising forming the collector regions of the vertical transistors and base regions of the lateral transistors from a common semiconductor region.
Claim 5
Dependent Claim 52 words
The method of claim 3 further comprising providing at least one field effect transistor having current carrying terminals connected to the base region of at least one vertical transistor and the emitter region of the same vertical transistor, and having a gate region coupled to the collector of the same vertical transistor.
Claim 6
Dependent Claim 108 words
The method of claim 4 further comprising grouping together the emitter region of the first lateral transistor and the collector region of the second lateral transistor in a substantially adjacent but spaced apart relationship to form a first emitter-collector pair, and the emitter region of the second lateral transistor and the collector regions of the first lateral transistor in a substantially adjacent but spaced apart relationship to form a second emitter-collector pair, further grouping the pairs in a substantially parallel adjacent spaced apart relationship, and substantially covering a periphery of each pair by a separate metallic electric field distributing conductor to enhance the blocking voltage of each pair.

References Cited (Backward Citations)

US3427512A Cited
US3432731A Cited
US3812405A Cited
US3831187A Cited
US4015143A Cited
US4224634A Cited
US4084110A Cited
US4100565A Cited
US4396932A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1987-07-10 1988-01-09 1988-07-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1991-07-10 1992-01-09 1992-07-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1995-07-10 1996-01-09 1996-07-10 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag