Dielectrically isolated high voltage semiconductor devices

Claim 2

An integrated circuit including a high voltage semiconductor device comprising a polycrystalline semiconductor substrate (10), a region of single crystalline semiconductor (11) the bulk of which has a first conductivity type formed at a major surface of said substrate, and a localized region (e.g., 15,) formed at the surface of said single crystalline region, characterized in that said device further comprises a semi-insulating layer (13) between said substrate and single crystalline region, said semi-insulating layer having trapping states capable of taking on charge from said single crystalline region and thereby shield said localized surface region from the potential of the substrate when a bias is supplied thereto.

Claim 3

The circuit according to claim 1 wherein the localized surface region (16, 17) has a conductivity type opposite to that of the bulk of said single crystalline region.

Claim 4

The circuit according to claim 1 wherein the localized surface region (14, 15) has the same conductivity type as the bulk of said single crystalline region but a higher impurity concentration.

Claim 5

The circuit according to claim 1 wherein the doping concentration of the bulk of the single crystalline region is less than 10 16 cm -3 .

Claim 6

The circuit according to claim 1 further comprising a dielectric layer (12) disposed between the substrate and the semi-insulating layer.

Claim 7

The circuit according to claim 1 wherein the thickness of the semi-insulating layer is within the range 0.05-20 μm.

Claim 8

The circuit according to claim 1 wherein the dielectric strength of the semi-insulating layer is greater than 2×10 5 volts/cm.

Claim 9

The circuit according to claim 1 wherein the resistivity of the semi-insulating layer is within the 10 4 -10 12 ohm-cm.

Claim 10

The circuit according to claim 1 wherein the concentration of trapping states in the layer is sufficient to take on charge from the single crystalline region in an amount of at least 5×10 11 electronic charges/cm 2 .

Claim 11

The circuit according to claim 1 wherein the semi-insulating layer comprises silicon doped with oxygen.

Claim 12

The circuit according to claim 10 wherein the doping concentration of oxygen lies within the range 10-40 atomic percent.

Claim 13

The circuit according to claim 1 wherein the semi-insulating layer is formed selectively between the side walls of the single crystalline region and the substrate.

Claim 14

The circuit according to claim 1 wherein there is included at the surface of said single crystalline region first and second localized regions (14 and 15) of the same conductivity type but higher doping concentration than the bulk of the single crystalline region, a third localized region (16) of opposite conductivity type disposed between the first and second regions, a fourth localized region (17) formed within the boundaries of the second region, electrical contacts to said first and fourth regions (19 and 20) and a gate electrode making electrical contact to the third region to form a gated diode switch in the single crystalline region.

Claim 15

The circuit according to claim 1 wherein there is included at the surface of said single crystalline region a first localized region (37 of FIG. 7) of the same conductivity type but higher doping concentration than the bulk of the single crystalline region, a second localized region (35) of opposite conductivity type surrounding said first region, a third localized region (36) of opposite conductivity type spaced from said first and second regions, a fourth localized region of the same conductivity type but higher doping concentration than the bulk of the single crystalline region surrounding said third localized region, electrical contacts (39 and 40) to said first and third regions, and a gate contact (41) to said second region to form a controlled rectifier in said single crystalline region.

Claim 16

The circuit according to claim 1 wherein there is formed at the surface of the single crystalline region first and second localized regions (54 and 55 of FIG. 8) of the same conductivity type but higher doping concentration than the bulk of the single crystalline region, a third localized region (56) of opposite conductivity type which is electrically coupled to said second localized region, and electrical contacts to said regions so as to form a pinched resistor in said single crystalline region.

Claim 17

A high voltage semiconductor device comprising a polycrystalline silicon substrate (10), a region of single crystalline silicon (11) the bulk of which has a first conductivity type and a doping concentration of less than 1×10 16 cm -3 formed at a major surface of said substrate, a localized region (e.g., 15) formed at the surface of said single crystalline region, and a dielectric layer (12) separating said single crystalline region from said substrate, characterized in that said device further comprises between the dielectric layer and the single crystalline region a layer (13) having a thickness of 0.05-5 μm comprising silicon which is doped with oxygen to a concentration of 10-40 atomic percent so as to form trapping states in said layer capable of taking on charge from said single crystalline region and thereby shield said localized surface region from the potential of the substrate when a bias is supplied thereto.

Claim 18

A high voltage semiconductor device comprising a polycrystalline silicon substrate (10), a region of single crystalline silicon (11) the bulk of which has a first conductivity type and a doping concentration of less than 1×10 16 cm -3 formed at a major surface of said substrate, a localized region (e.g., 15) formed at the surface of said single crystalline region, and a dielectric layer (12) separating said single crystalline region from said substrate, characterized in that said device further comprises between the dielectric layer and the single crystalline region a layer (13) having a thickness of 0.05-5 μm comprising silicon which is doped with oxygen to a concentration of 10-40 atomic percent so as to form trapping states in said layer capable of taking on charge from said single crystalline region and thereby shield said localized surface region from the potential of the substrate when a bias is supplied thereto.

Claim 19

A high voltage semiconductor device comprising a polycrystalline silicon substrate (10), a region of single crystalline silicon (11) the bulk of which has a first conductivity type with a doping concentration of less than 1×10 16 cm -3 formed at a major surface of said substrate, first and secod localized regions (14 and 15) formed at the surface of the single crystalline region having the same conductivity type but higher doping concentration than the bulk of the single crystalline region, a third localized region (16) of opposite conductivity type formed at the surface of the single crystalline region between the first and second regions, a fourth localized region (17) of opposite conductivity type formed at the surface of the single crystalline region within the boundaries of the second region, electrical contacts to said first and fourth regions (19 and 20), a gate electrode (21) which makes electrical contact to the third region and a dielectric layer (12) comprising SiO 2 separating said single crystalline region from said substrate characterized in that said device further comprises between the dielectric layer and the single crystalline region a layer (13) having a thickness of 0.05-5 μm comprising silicon doped with oxygen to a concentration of 10-40 atomic percent to produce a layer having a dielectric strength of greater than 2×10 5 volts/cm, and trapping states capable of taking on charge from said single crystalline region in excess of 5×10 11 electronic charges/cm.sup. 2 and thereby shield the localized surface regions from the potential of the substrate when a bias is supplied thereto.

Claim 20

A high voltage semiconductor device comprising a polycrystalline silicon substrate (10), a region of single crystalline silicon (11) the bulk of which has a first conductivity type with a doping concentration of less than 1×10 16 cm -3 formed at a major surface of said substrate, first and secod localized regions (14 and 15) formed at the surface of the single crystalline region having the same conductivity type but higher doping concentration than the bulk of the single crystalline region, a third localized region (16) of opposite conductivity type formed at the surface of the single crystalline region between the first and second regions, a fourth localized region (17) of opposite conductivity type formed at the surface of the single crystalline region within the boundaries of the second region, electrical contacts to said first and fourth regions (19 and 20), a gate electrode (21) which makes electrical contact to the third region and a dielectric layer (12) comprising SiO 2 separating said single crystalline region from said substrate characterized in that said device further comprises between the dielectric layer and the single crystalline region a layer (13) having a thickness of 0.05-5 μm comprising silicon doped with oxygen to a concentration of 10-40 atomic percent to produce a layer having a dielectric strength of greater than 2×10 5 volts/cm, and trapping states capable of taking on charge from said single crystalline region in excess of 5×10 11 electronic charges/cm.sup. 2 and thereby shield the localized surface regions from the potential of the substrate when a bias is supplied thereto.