Semiconductor device with a semiconductor substrate having dielectrically isolated functional regions

Claim 2

A semiconductor device comprising, in combination: a polycrystalline semiconductor substrate; and a first dielectric insulating layer selectively disposed on a plurality of portions of a first surface of said substrate; a plurality of functional monocrystalline semiconductor regions respectively disposed on said selectively disposed first dielectric insulating layer so as to be insulated from the respective portions of said first surface of said substrate; and wherein each monocrystalline semiconductor region is electrically isolated from adjacent monocrystalline semiconductor regions by a polycrystalline semiconductor region therebetween, which polycrystalline semiconductor region is electrically isolated from both said monocrystalline regions and said substrate; and wherein the angle formed by the side portions of a monocrystalline region and the first dielectric insulating layer on which said monocrystalline region is disposed is an obtuse angle.

Claim 3

A semiconductor device according to claim 1, wherein said polycrystalline semiconductor region is electrically isolated from said monocrystalline region by a second dielectric layer disposed therebetween and contiguous with said first dielectric layer.

Claim 4

A semiconductor device according to claim 2, wherein said polycrystalline semiconductor region is electrically isolated from said substrate by a third dielectric layer disposed therebetween and contiguous with said second dielectric layer.

Claim 5

A semiconductor device according to claim 3, wherein said first and third dielectric layers are substantially coplanar.

Claim 6

A semiconductor device according to claim 2, wherein said polycrystalline semiconductor region is electrically isolated from said substrate by a third dielectric layer disposed therebetween and contiguous with said first dielectric layer.

Claim 7

A semiconductor device according to claim 5, wherein said polycrystalline semiconductor substrate extends between said monocrystalline regions and further including a fourth dielectric layer contiguous with the side surfaces of selected ones of said monocrystalline regions and electrically isolating said substrate from the side surfaces of said selected ones of said monocrystalline regions.

Claim 8

A semiconductor device according to claim 5, wherein said polycrystalline semiconductor substrate extends between said monocrystalline regions and wherein the side surfaces of each of said monocrystalline regions are surrounded by a polycrystalline semiconductor region.

Claim 9

A semiconductor device according to claim 5, wherein each monocrystalline semiconductor region is further electrically isolated from adjacent monocrystalline semiconductor regions by a further polycrystalline semiconductor region therebetween, which further polycrystalline semiconductor region is electrically isolated from said monocrystalline regions, said substrate and the first mentioned polycrystalline semiconductor region.

Claim 10

A semiconductor device according to claim 8, wherein each monocrystalline semiconductor region is additionally electrically isolated from adjacent monocrystalline semiconductor regions by an additional polycrystalline semiconductor region therebetween, which additional polycrystalline semiconductor region is electrically isolated from said monocrystalline regions, said substrate, said first mentioned polycrystalline semiconductor region and said further polycrystalline semiconductor region.

Claim 11

A semiconductor device according to claim 2, wherein the thickness of said polycrystalline semiconductor region is greater than the thickness of a monocrystalline semiconductor region.

Claim 12

A semiconductor device according to claim 10, wherein said polycrystalline semiconductor region is electrically isolated from said substrate by a third dielectric layer disposed therebetween and contiguous with said first dielectric layer.

Claim 13

A semiconductor device according to claim 11, wherein the thickness of said polycrystalline semiconductor region is greater than the thickness of said substrate.

Claim 14

A semiconductor device comprising, in combination: a polycrystalline semiconductor substrate; and a first dielectric insulating layer selectively disposed on a plurality of portions of a first surface of said substrate; a plurality of functional monocrystalline semiconductor regions respectively disposed on said selectively disposed first dielectric insulating layer so as to be insulated from the respective portions of said first surface of said substrate; and wherein each monocrystalline semiconductor region is electrically isolated from adjacent monocrystalline semiconductor regions by a polycrystalline semiconductor region therebetween, which polycrystalline semiconductor region is electrically isolated from said monocrystalline regions and is electrically isolated from said substrate by a second dielectric layer disposed therebetween, contiguous with said first dielectric layer and extending to a second surface of said substrate, opposite said first surface thereof.

Claim 15

A semiconductor device comprising, in combination: a polycrystalline semiconductor substrate; and a first dielectric insulating layer selectively disposed on a plurality of portions of a first surface of said substrate; a plurality of functional monocrystalline semiconductor regions respectively disposed on said selectively disposed first dielectric insulating layer so as to be insulated from the respective portions of said first surface of said substrate; and wherein each monocrystalline semiconductor region is electrically isolated from adjacent monocrystalline semiconductor regions by a polycrystalline semiconductor region therebetween, which polycrystalline semiconductor region is electrically isolated from said monocrystalline regions and is electrically isolated from said substrate by a second dielectric layer disposed therebetween, contiguous with said first dielectric layer and extending to a second surface of said substrate, opposite said first surface thereof.

Claim 16

A semiconductor device comprising, in combination: a polycrystalline semiconductor substrate; and a first dielectric insulating layer selectively disposed on a plurality of portions of a first surface of said substrate; a plurality of functional monocrystalline semiconductor regions respectively disposed on said selectively disposed first dielectric insulating layer so as to be insulated from the respective portions of said first surface of said substrate; and wherein each monocrystalline semiconductor region is electrically isolated from adjacent monocrystalline semiconductor regions by a polycrystalline semiconductor region therebetween which polycrystalline semiconductor region is electrically isolated from said monocrystalline semiconductor regions by a second dielectric layer circumferentially surrounding and contiguous to the side surfaces of each monocrystalline region and is electrically isolated from said substrate by a third dielectric layer disposed therebetween and contiguous to said first dielectric layer, so that said polycrystalline semiconductor region is electrically floating relative to said substrate and said monocrystalline regions, and wherein said polycrystalline semiconductor region is comprised of a plurality of polycrystalline semiconductor region portions surrounding respective monocrystalline regions and electrically isolated from each other by respective dielectric layers therebetween, which respective dielectric layers extend from said third layer to the external surface of said polycrystalline region.

Claim 17

A semiconductor device comprising, in combination: a polycrystalline semiconductor substrate; and a first dielectric insulating layer selectively disposed on a plurality of portions of a first surface of said substrate; a plurality of functional monocrystalline semiconductor regions respectively disposed on said selectively disposed first dielectric insulating layer so as to be insulated from the respective portions of said first surface of said substrate; and wherein each monocrystalline semiconductor region is electrically isolated from adjacent monocrystalline semiconductor regions by a polycrystalline semiconductor region therebetween which polycrystalline semiconductor region is electrically isolated from said monocrystalline semiconductor regions by a second dielectric layer circumferentially surrounding and contiguous to the side surfaces of each monocrystalline region and is electrically isolated from said substrate by a third dielectric layer disposed therebetween and contiguous to said first dielectric layer, so that said polycrystalline semiconductor region is electrically floating relative to said substrate and said monocrystalline regions, and wherein said polycrystalline semiconductor region is comprised of a plurality of polycrystalline semiconductor region portions surrounding respective monocrystalline regions and electrically isolated from each other by respective dielectric layers therebetween, which respective dielectric layers extend from said third layer to the external surface of said polycrystalline region.