US3722079A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for forming buried layers to reduce collector resistance in top contact transistors
Assignee: Radiation Inc
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Filing: 1970-06-05
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Granted: 1973-03-27
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Expires: 1990-06-05
Abstract
Abstract A buried layer in an integrated circuit structure is formed by one-step deposition (epitaxial or diffusion) of heavily doped silicon over the bottom surface of a wafer in which islandseparating moats have been etched. The buried layer is thus uniformly provided both at the bottom and along the sides of the finished islands. In the formation of a transistor in the island, a collector contact diffusion layer is diffused through a mask aperture configured and spaced relative to the island center to assure intersection between this diffusion layer and buried layer. In addition the collector contact is deposited through another mask aperture spaced and configured relative to the island center to assure that the collector contact is in contact only with the portion of the collector contact diffusion layer residing within the island edges.
Inventors
- 👤 J Beasom
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 05:30
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/019; H10W10/10; H10W20/00; H10W20/01; H10W20/021; H10W20/20; Y; Y10; Y10S; Y10S148/00; Y10S148/036; Y10S148/049; Y10S148/085; Y10S148/122
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
21 words
The process according to claim 1, further including forming a circuit component within each of at least some of said islands.
Claim 2
Dependent Claim
38 words
The process according to claim 2, wherein at least one said circuit component is a transistor, and said portion of the island with which low resistance contact is to be made is the collector region of said transistor.
Claim 3
Dependent Claim
22 words
The process according to claim 1, wherein said island surface boundaries vary even as between islands of nominally the same desired size.
Claim 4
Dependent Claim
46 words
The process according to claim 1, wherein said low resistivity restrictive region bounds both sides of said dielectric isolation layer of at least some of said islands as a consequence of the respective island having been fabricated with a surface boundary less than said maximum boundary.
Claim 5
Dependent Claim
48 words
The process according to claim 1, wherein said dielectric isolation layer divides said low resistivity restricted regions of at least some of said islands, so that no direct electrical continuity exists between the portions of the restricted region within and outside of the boundary of any given island.
Claim 6
Dependent Claim
20 words
The process according to claim 1, wherein said semiconductor material is silicon, and said dielectric isolation layer is silicon dioxide.
Claim 7
Dependent Claim
17 words
The process according to claim 7, wherein said silicon dioxide layer is thinner than said border layer.
Claim 8
Dependent Claim
39 words
The process according to claim 8, wherein said portion of each single crystal island to which said low resistance contact is to be made and each of said border layers and said restricted regions is of N type conductivity.
Claim 9
Dependent Claim
171 words
In a Process for fabricating integrated circuits in a plurality of single crystal semiconductor islands embedded in and sharing a planar surface of a substrate, said islands electrically isolated from one another and from said substrate by a dielectric layer, and wherein the size of the islands at said surface may vary within predetermined maximum and minimum limits as a consequence of allowable production variations, the steps of: providing in at least some of said islands a layer of low resistivity single crystal semiconductor material in proximity to the dielectric layer for the respective island, said low resistivity layer extending from the bottom of said island to said surface, and forming at said surface of each of said islands in which said low resistivity layer is provided a restricted region of low resistivity single crystal semiconductor material extending over an area including said maximum and minimum limits for one edge of the respective island, to intersect the respective low resistivity layer regardless of variation of island surface size between said limits.
Claim 10
Dependent Claim
37 words
The process according to claim 10, further including forming a conductive layer atop an area of said low resistivity restricted region wholly within the minimum limit of extent of said edge of each of the respective islands.
Claim 11
Dependent Claim
59 words
The process according to claim 11, wherein: said dielectric layer divides the low resistivity restricted region associated with at least some of said islands into first and second electrically isolated portions to preclude electrical continuity between the portion within the actual boundary and the portion outside the actual boundary of an island whose boundary is inside said maximum limit.
Claim 12
Dependent Claim
190 words
A process for producing low resistance contact with a preselected region of a single crystal semiconductor island electrically isolated from other islands within a substrate but sharing a common planar surface therewith, and wherein the size of the islands at said surface may vary within predetermined maximum and minimum limits as a consequence of allowable production variations, which comprises: forming in each said island which is to have said low resistance contact a buried layer of low resistivity single crystal semiconductor material penetrating the island from the surface thereof to that preselected region with which low resistance contact is to be established, and establishing at the surface simultaneously for each of at least a plurality of islands having said buried layer a further layer of low resistivity single crystal semiconductor material intersecting the respective buried layer, each said further layer occupying an area of the surface associated with a respective island sufficiently large to intersect the respective buried layer despite said island-to-island variations in the location of the buried layer at the surface and sufficiently small to preclude conductive contact with the further layer respectively associated with any adjacent island.
Claim 13
Dependent Claim
68 words
The process according to claim 13, further including applying to each said further layer a conductive layer for electrical contact therewith and therefore with said preselected region to which said buried layer penetrates, said conductive layer restricted to overlie an area of said further layer wholly within the minimum allowable distance between the center of the island and the respective buried layer at the surface of that island.
Claim 14
Independent Claim
359 words
The method of fabricating an integrated circuit structure of the type wherein a low-resistance buried layer underlies one or more isolated component-containing islands, said method including the steps of: etching V-groove moats in a planar surface of a single crystal semiconductor wafer to designate the locations of said islands, forming at said surface and the surfaces of said moats a thin layer of single crystal semiconductor material of lower resistivity than the original semiconductor wafer, to constitute said buried layer, growiNg a dielectric isolation layer over said buried layer, depositing polycrystalline semiconductor material on said isolation layer to fill said moats and cover said surface, lapping back the opposite surface of said wafer to a planar surface to expose said polycrystalline semiconductor material in said moats surrounding the dielectric isolation layer bounding the respective islands, said islands thereby having dimensions at said planar surface at which they are exposed which vary between predetermined allowable maximum and minimum limits depending upon the extent of the actual backlapping of said opposite surface of said wafer, diffusing impurities through a mask aperture associated with each island and configured to form a contact diffusion layer which extends from a point on the island surface within the minimum allowable surface boundary to a point outside the maximum allowable surface boundary of each respective island, irrespective of the actual island boundary, so that the contact diffusion layer of any given island is assured of contacting the buried layer of that island regardless of possible variations in the island surface size from a predetermined nominal size, some of said islands thereby having an associated contact diffusion layer which is split by the dielectric isolation layer into a segment within the actual island boundary and contacting the buried layer and a segment outside the island boundary and isolated therefrom, and depositing a conductive contact layer atop said contact diffusion layer through a further mask aperture associated with each island having a contact diffusion layer, wherein said further mask aperture is positioned and configured to form said contact layer entirely on the portion of said contact diffusion layer within said minimum allowable surface boundary of the respective island.
References Cited (Backward Citations)
US3381182A
Cited
US3370995A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-03-26 | 1976-09-25 | 1977-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-03-26 | 1980-09-25 | 1981-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-03-26 | 1984-09-25 | 1985-03-27 | $7700.00 | Window Closed / Lapsed |