Insulated gate field effect transistor

Claim 2

An insulated gate field effect transistor, comprising: an insulator body having a generally planar major surface; a semiconductor layer of a first conductivity type formed on said insulator body major surface, said semiconductor layer having a generally planar, major surface lying parallel to said insulator body major surface; a source region of a second conductivity type, opposite of that of said first conductivity type, formed in said semiconductor layer along said major surface of said semiconductor layer; a drain region of said second conductivity type formed in said semiconductor layer along said major surface of said semiconductor layer and spaced from said source region with a channel region lying therebetween; an extension region of said second conductivity type formed in said semiconductor layer and extending from one of said source and drain regions to said channel region, said extension region having an impurity concentration lower than that of said one of said source and drain regions, one surface of said extension region being coincident with said major surface of said semiconductor layer, a second surface of said extension region being generally parallel to said insulator body surface and spaced therefrom such that a portion of said semiconductor layer lies between said second surface and said insulator body major surface, the total amount of effective impurity of said second conductivity type contained in said extension region being within a difference of 20 percent of the total amount of effective impurity of said first conductivity type contained in said semiconductor layer portion lying between said extension region and said insulator body; a first insulating film formed on the entire first surface of said extension region; a gate insulating film formed on said channel region; and a gate electrode formed on said gate film.

Claim 3

An insulated gate field effect transistor of claim 1, in which a total amount of effective impurity of said second conductivity type contained in said extension region differs from a total amount of effective impurity of said first conductivity type contained in said semiconductor layer portion located between said extension region and said insulator body by -10% or less, whereby the inverse breakdown voltage between said one of said source and drain regions and said semiconductor layer may withstand a voltage of 400 V or higher.

Claim 4

An insulated gate field effect transistor of claim 1, in which the length of said extension region as measured in a direction parallel to said insulator body major surface is larger than the thickness of the semiconductor layer portion lying between said extension region and said insulator body as measured in a direction perpendicular to said insulator body major surface.

Claim 5

An insulated gate field effect transistor of claim 1, in which the impurity concentration per unit area of said extension region as measured along a plane lying parallel to said insulator body major surface is 3×10 12 cm -2 or lower.

Claim 6

An insulated gate field effect transistor of claim 1, in which said insulator body is formed of sapphire and said semiconductor layer is a layer grown on said sapphire.

Claim 7

An insulated gate field effect transistor of claim 1, in which said insulator body is a second insulating film provided on a polycrystalline silicon base body, and said semiconductor layer is a monocrystalline silicon and provided on said second insulating film.

Claim 8

An insulated gate field effect transistor of claim 1, in which said gate insulating film and said first insulating film are continuously formed.

Claim 9

An insulated gate field effect transistor of claim 1, in which said source region, said drain region and said channel region are arranged in parallel to each other as viewed along a plane lying parallel to said insulating body major surface.

Claim 10

An insulated gate field effect transistor of claim 1, in which said extension region, said channel region and said source region are arranged in a concentric ring-shaped pattern about said drain region at the center as viewed along a plane lying parallel to said insulating body major surface.

Claim 11

An integrated circuit device comprising an insulating member having a generally planar major surface and a plurality of insulated gate field effect transistors formed thereon, each of said transistors being isolated from the remaining said transistors and comprising: a semiconductor layer of a first conductivity type formed on said insulator body major surface, said semiconductor layer having a generally planar, major surface lying parallel to said insulator body major surface; a source region of a second conductivity type, opposite of that of said first conductivity type, formed in said semiconductor layer along said major surface of said semiconductor layer; a drain region of said second conductivity type formed in said semiconductor layer along said major surface of said semiconductor layer and spaced from said source region with a channel region lying therebetween; an extension region of said second conductivity type formed in said semiconductor layer and extending from one of said source and drain regions to said channel region, said extension region having an impurity concentration lower than that of said one of said source and drain regions, one surface of said extension region being coincident with said major surface of said semiconductor layer, a second surface of said extension region being generally parallel to said insulator body surface and spaced therefrom such that a portion of said semiconductor layer lies between said second surface and said insulator body major surface, the total amount of effective impurity of said second conductivity type contained in said extension region being within a difference of 20 percent of the total amount of effective impurity of said first conductivity type contained in said semiconductor layer portion lying between said extension region and said insulator body; a first insulating film formed on the entire first surface of said extension region; a gate insulating film formed on said channel region; and a gate electrode formed on said gate film.

Claim 12

An integrated circuit device comprising an insulating member having a generally planar major surface and a plurality of insulated gate field effect transistors formed thereon, each of said transistors being isolated from the remaining said transistors and comprising: a semiconductor layer of a first conductivity type formed on said insulator body major surface, said semiconductor layer having a generally planar, major surface lying parallel to said insulator body major surface; a source region of a second conductivity type, opposite of that of said first conductivity type, formed in said semiconductor layer along said major surface of said semiconductor layer; a drain region of said second conductivity type formed in said semiconductor layer along said major surface of said semiconductor layer and spaced from said source region with a channel region lying therebetween; an extension region of said second conductivity type formed in said semiconductor layer and extending from one of said source and drain regions to said channel region, said extension region having an impurity concentration lower than that of said one of said source and drain regions, one surface of said extension region being coincident with said major surface of said semiconductor layer, a second surface of said extension region being generally parallel to said insulator body surface and spaced therefrom such that a portion of said semiconductor layer lies between said second surface and said insulator body major surface, the total amount of effective impurity of said second conductivity type contained in said extension region being within a difference of 20 percent of the total amount of effective impurity of said first conductivity type contained in said semiconductor layer portion lying between said extension region and said insulator body; a first insulating film formed on the entire first surface of said extension region; a gate insulating film formed on said channel region; and a gate electrode formed on said gate film.

Claim 13

An integrated circuit device of claim 10, in which said insulator member is a sapphire substrate and each of said semiconductor layers is provided thereon in the form of an individual island.

Claim 14

An insulated gate field effect transistor, comprising: an insulator body; a semiconductor layer of one conductivity type on a surface of said insulator body; a source region and drain region, each of the opposite conductivity type, formed in said semiconductor layer and extending from a first major surface of said semiconductor layer to a second major surface of said semiconductor layer which is adjacent said surface of said insulator body; an extension region of said opposite conductivity type formed in said semiconductor layer and extending from one of said source and drain regions towards the other of said source and drain regions, said extension region having an impurity concentration lower than that of said one of said source and drain regions, said extension region extending from said first major surface of said semiconductor layer into said semiconductor layer but not reaching said insulator body surface such that a portion of said semiconductor layer is located between said extension region and said insulator body; a channel region positioned between said extension region and the other of said source and drain regions; a gate insulating film formed on said channel region; and a gate electrode formed on said gate insulating film and not extending over said extension region.

Claim 15

An insulated gate field effect transistor, comprising: an insulator body; a semiconductor layer of one conductivity type on a surface of said insulator body; a source region and drain region, each of the opposite conductivity type, formed in said semiconductor layer and extending from a first major surface of said semiconductor layer to a second major surface of said semiconductor layer which is adjacent said surface of said insulator body; an extension region of said opposite conductivity type formed in said semiconductor layer and extending from one of said source and drain regions towards the other of said source and drain regions, said extension region having an impurity concentration lower than that of said one of said source and drain regions, said extension region extending from said first major surface of said semiconductor layer into said semiconductor layer but not reaching said insulator body surface such that a portion of said semiconductor layer is located between said extension region and said insulator body; a channel region positioned between said extension region and the other of said source and drain regions; a gate insulating film formed on said channel region; and a gate electrode formed on said gate insulating film and not extending over said extension region.

Claim 16

An insulated gate field effect transistor of claim 12, in which a total amount of effective impurity of the opposite conductivity type contained in said extension region differs from a total amount of effective impurity of said one conductivity type contained in said portion of said semiconductor layer only by ±20% or less.

Claim 17

An insulated gate field effect transistor of claim 12, in which a total amount of effective impurity of the opposite conductivity type contained in said extension region differs from a total amount of effective impurity of said one conductivity type contained in said portion of said semiconductor layer only by ±10% or less, whereby the inverse breakdown voltage between said one of said drain and source regions and said semiconductor layer may withstand a voltage of 400 V or higher.

Claim 18

An insulated gate field effect transistor, comprising: an insulator body; a semiconductor layer of a first conductivity type on a surface of said insulator body; a source region and a drain region, each of a second conductivity type opposite that of said first conductivity type, formed in said semiconductor layer at spaced locations along a major surface of said semiconductor layer; an extension region of said second conductivity type formed in said semiconductor layer and having a first surface lying along said major surface and a second surface spaced from said major surface and forming a PN junction with a portion of said semiconductor layer, said PN junction being substantially parallel with said major surface, said extension region extending from one of said source and drain regions but stopping short of said other of said source and drain regions such that a channel region is located between said extension and said other of said source and drain regions, said extension region having an impurity concentration lower than that of said source and drain regions; an insulating gate film formed on the entire surface of said first surface; a gate insulating film formed on said channel region; and a gate electrode formed on said insulating film, one end of said gate electrode being substantially aligned with that end of said extension region which is remote from said one of said source and drain regions.

Claim 19

An insulated gate field effect transistor, comprising: an insulator body; a semiconductor layer of a first conductivity type on a surface of said insulator body; a source region and a drain region, each of a second conductivity type opposite that of said first conductivity type, formed in said semiconductor layer at spaced locations along a major surface of said semiconductor layer; an extension region of said second conductivity type formed in said semiconductor layer and having a first surface lying along said major surface and a second surface spaced from said major surface and forming a PN junction with a portion of said semiconductor layer, said PN junction being substantially parallel with said major surface, said extension region extending from one of said source and drain regions but stopping short of said other of said source and drain regions such that a channel region is located between said extension and said other of said source and drain regions, said extension region having an impurity concentration lower than that of said source and drain regions; an insulating gate film formed on the entire surface of said first surface; a gate insulating film formed on said channel region; and a gate electrode formed on said insulating film, one end of said gate electrode being substantially aligned with that end of said extension region which is remote from said one of said source and drain regions.

Claim 20

An insulated gate field effect transistor, comprising: an insulator body; a semiconductor layer of one conductivity type on a surface of said insulator body; a source region and drain region, each of the opposite conductivity type, formed in said semiconductor layer and extending from a first major surface of said semiconductor layer to a second major surface of said semiconductor layer which is adjacent said surface of said insulator body; an extension region of said opposite conductivity type formed in said semiconductor layer and extending from one of said source and drain regions towards the other of said source and drain regions, said extension region having an impurity concentration lower than that of said one of said source and drain regions, said extension region extending from said first major surface of said semiconductor layer into said semiconductor layer but not reaching said insulator body surface such that a portion of said semiconductor layer is located between said extension region and said insulator body, the total amount of effective impurity of said opposite conductivity type contained in said extension region being less than 120 percent and more than 80 percent of the total amount of effective impurity of said first conductivity type contained in said portion of said semiconductor layer located between said extension region and said insulator body; a channel region positioned between said extension region and the other of said source and drain regions; a gate insulating film formed on said channel region; and a gate electrode formed on said gate insulating film and not extending over said extension region.

Claim 21

An insulated gate field effect transistor, comprising: an insulator body; a semiconductor layer of one conductivity type on a surface of said insulator body; a source region and drain region, each of the opposite conductivity type, formed in said semiconductor layer and extending from a first major surface of said semiconductor layer to a second major surface of said semiconductor layer which is adjacent said surface of said insulator body; an extension region of said opposite conductivity type formed in said semiconductor layer and extending from one of said source and drain regions towards the other of said source and drain regions, said extension region having an impurity concentration lower than that of said one of said source and drain regions, said extension region extending from said first major surface of said semiconductor layer into said semiconductor layer but not reaching said insulator body surface such that a portion of said semiconductor layer is located between said extension region and said insulator body, the total amount of effective impurity of said opposite conductivity type contained in said extension region being less than 120 percent and more than 80 percent of the total amount of effective impurity of said first conductivity type contained in said portion of said semiconductor layer located between said extension region and said insulator body; a channel region positioned between said extension region and the other of said source and drain regions; a gate insulating film formed on said channel region; and a gate electrode formed on said gate insulating film and not extending over said extension region.

Claim 22

An insulated gate field effect transistor, comprising: an insulator body; a semiconductor layer of a first conductivity type on a surface of said insulator body; a source region and a drain region, each of a second conductivity type opposite that of said first conductivity type, formed in said semiconductor layer at spaced locations along a major surface of said semiconductor layer; an extension region of said second conductivity type formed in said semiconductor layer and having a first surface lying along said major surface and a second surface spaced from said major surface and forming a PN junction with a portion of said semiconductor layer, said PN junction being substantially parallel with said major surface, said extension region extending from one of said source and drain regions but stopping short of said other of said source and drain regions such that a channel region is located between said extension and said other of said source and drain regions, said extension region having an impurity concentration lower than that of said source and drain regions, the total amount of effective impurity of said second conductivity type contained in said extension region being within a difference of 20 percent of the total amount of effective impurity of said first conductivity type contained in said portion of said semiconductor layer lying between said extension region and said insulator body; an insulating gate film formed on the entire surface of said first surface; a gate insulating film formed on said channel region; and a gate electrode formed on said insulating film, one end of said gate electrode being substantially aligned with that end of said extension region which is remote from said one of said source and drain regions.

Claim 23

An insulated gate field effect transistor, comprising: an insulator body; a semiconductor layer of a first conductivity type on a surface of said insulator body; a source region and a drain region, each of a second conductivity type opposite that of said first conductivity type, formed in said semiconductor layer at spaced locations along a major surface of said semiconductor layer; an extension region of said second conductivity type formed in said semiconductor layer and having a first surface lying along said major surface and a second surface spaced from said major surface and forming a PN junction with a portion of said semiconductor layer, said PN junction being substantially parallel with said major surface, said extension region extending from one of said source and drain regions but stopping short of said other of said source and drain regions such that a channel region is located between said extension and said other of said source and drain regions, said extension region having an impurity concentration lower than that of said source and drain regions, the total amount of effective impurity of said second conductivity type contained in said extension region being within a difference of 20 percent of the total amount of effective impurity of said first conductivity type contained in said portion of said semiconductor layer lying between said extension region and said insulator body; an insulating gate film formed on the entire surface of said first surface; a gate insulating film formed on said channel region; and a gate electrode formed on said insulating film, one end of said gate electrode being substantially aligned with that end of said extension region which is remote from said one of said source and drain regions.