Field effect transistor and method of construction thereof

Claim 1

The method of making a field effect transistor comprising: forming on an insulating substrate at least one island comprising semi-conductor material of a first conductivity type, said island being in the form of a layer 0.8 to 1.2 micrometers in thickness; growing over the outer surface of said island a first, upper, thin masking layer 150 to 250 nanometers in thickness; removing two separated regions of said first upper layer, leaving an intermediate region of this layer as a mask; diffusing into the thus exposed separated regions of said wafer a material increasing the conductivity of the thus exposed separated regions, the increase being in the same polarity direction as the existing polarity of said semi-conductor material to thus create two separated enhanced discrete polarity regions comprising source and drain regions; removing the balance of said first insulating layer and growing a second insulating layer over the outer body of said wafer to a thickness of 800 to 1,000 nanometers, then etching a window in a small central portion, smaller than but within the area in which said intermediate region of said first layer was located, were a reduced thickness of 30 to 40 nanometers is grown to define a gate region; bombarding said gate region with an opposite, second, polarity type ion bombardment, the dosage of said bombardment being that required to exceed the original degree of impurity concentration in said wafer to a selected degree, whereby there is created a gate region of a second polarity separated from said source and drain regions by modified regions of said first polarity type, but of lesser conductivity than said source and drain regions; removing said second layer over said gate region of said wafer and cleaning the thus exposed surface of said wafer; growing a third insulating layer to a thickness of 100 to 110 nanometers over said gate region; removing said second layer over said source and drain regions, creating openings for source and drain contacts; and depositing conductive electrodes to thus exposed source and drain openings in said second layer and on said third layer over said gate region.

Claim 2

The method of making a field effect transistor comprising: forming on an insulating substrate at least one island comprising semi-conductor material of a first conductivity type, said island being in the form of a layer 0.8 to 1.2 micrometers in thickness; growing over the outer surface of said island a first, upper, thin masking layer 150 to 250 nanometers in thickness; removing two separated regions of said first upper layer, leaving an intermediate region of this layer as a mask; diffusing into the thus exposed separated regions of said wafer a material increasing the conductivity of the thus exposed separated regions, the increase being in the same polarity direction as the existing polarity of said semi-conductor material to thus create two separated enhanced discrete polarity regions comprising source and drain regions; removing the balance of said first insulating layer and growing a second insulating layer over the outer body of said wafer to a thickness of 800 to 1,000 nanometers, then etching a window in a small central portion, smaller than but within the area in which said intermediate region of said first layer was located, were a reduced thickness of 30 to 40 nanometers is grown to define a gate region; bombarding said gate region with an opposite, second, polarity type ion bombardment, the dosage of said bombardment being that required to exceed the original degree of impurity concentration in said wafer to a selected degree, whereby there is created a gate region of a second polarity separated from said source and drain regions by modified regions of said first polarity type, but of lesser conductivity than said source and drain regions; removing said second layer over said gate region of said wafer and cleaning the thus exposed surface of said wafer; growing a third insulating layer to a thickness of 100 to 110 nanometers over said gate region; removing said second layer over said source and drain regions, creating openings for source and drain contacts; and depositing conductive electrodes to thus exposed source and drain openings in said second layer and on said third layer over said gate region.