Patent US4860192A successfully refreshed from Google Patents.
US4860192A
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US
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Quadword boundary cache system
Assignee: Intergraph Corp
•
Filing: 1986-10-03
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Granted: 1989-08-22
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Expires: 2006-10-03
Abstract
Abstract In a cache memory system, multiple-word boundary registers, multiple-word line registers, and a multiple-word boundary detector system provide accelerated access of data contained within the cache memory within the multiple-word boundaries, and provides for effective prefetch of sequentially ascending locations of stored data from the cache memory. In an illustrated embodiment, the cache memory stores four words per addressable line of cache storage, and accordingly quad-word boundary registers determine boundary limits on quad-words, quad-word line registers store, in parallel, a selected line from the cache memory, and a quad-word boundary detector system determines when to prefetch the next set of quad-words from the cache memory for storage in the quad-word line registers.
Inventors
- 👤 Howard G. Sachs
- 👤 James Y. Cho
- 👤 Walter H. Hollingsworth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:10
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3814; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0846; G06F12/0848; G06F12/0862; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
166 words
A cache memory system comprising: an addressable cache memory, including means for storing a plurality of lines of a plurality of data words, the data words in each line being from contiguous sequential addresses in a main memory; first real address receiving means, coupled to the cache memory, for receiving a first real address portion from a CPU and for addressing a line of data in the cache memory with the first real address portion; a line register, coupled to the cache memory, for independently storing the plurality of data words from a line of data in the cache memory; line communicating means, coupled to the cache memory and to the line register, for communicating the addressed line of data to the line register; word receiving means for receiving a word stored in the line register; and word communicating means, coupled to the line register and to the word receiving means, for selectively communicating a word stored in the line register to the word receiving means.
Claim 2
Dependent Claim
166 words
A cache memory system comprising: an addressable cache memory, including means for storing a plurality of lines of a plurality of data words, the data words in each line being from contiguous sequential addresses in a main memory; first real address receiving means, coupled to the cache memory, for receiving a first real address portion from a CPU and for addressing a line of data in the cache memory with the first real address portion; a line register, coupled to the cache memory, for independently storing the plurality of data words from a line of data in the cache memory; line communicating means, coupled to the cache memory and to the line register, for communicating the addressed line of data to the line register; word receiving means for receiving a word stored in the line register; and word communicating means, coupled to the line register and to the word receiving means, for selectively communicating a word stored in the line register to the word receiving means.
Claim 3
Dependent Claim
68 words
The cache memory system according to claim 1 wherein virtual addresses of the data words in the line register define a boundary and further comprising: virtual address receiving means for receiving a virtual address from the CPU, the virtual address being associated with the first real address; and boundary detecting means, coupled to the virtual address receiving means, for detecting whether the virtual address is within the boundary.
Claim 4
Dependent Claim
42 words
The cache memory system according to claim 2 wherein the word communicating means is coupled to the boundary detecting means and communicates a data word from the line register to the word receiving means when the virtual address is within the boundary.
Claim 5
Dependent Claim
34 words
The cache memory system according to claim 3 wherein the word communicating means uses a portion of the first real address to select the data word to be communicated to the word receiving means.
Claim 6
Dependent Claim
50 words
The cache memory system according to claim 4 wherein the line communicating means is coupled to the boundary detecting means and communicates the plurality of data words in a next line of data in the cache memory to the line register when the virtual address is not within the boundary.
Claim 7
Dependent Claim
58 words
The cache memory system according to claim 5 wherein the boundary detecting means comprises: a boundary register for storing a starting address of the plurality of data words in a line of data; and a boundary comparator, coupled to the boundary register and to the virtual address receiving means, for comparing the virtual address to the starting address.
Claim 8
Dependent Claim
36 words
The cache memory system according to claim 6 wherein the cache memory further comprises: second real address storing means for storing a second real address associated with the plurality of words of data in each line.
Claim 9
Dependent Claim
69 words
The cache memory system according to claim 7 further comprising: translation means, coupled to the virtual address receiving means and to the word communicating means, for storing a plurality of lines of address information, each line corresponding to a line of data in the cache memory, each line storing a third real address corresponding to the virtual address, the third real address being communicated to the word communication means.
Claim 10
Dependent Claim
68 words
The cache memory according to claim 8 wherein the word communicating means further comprises: comparing means, coupled to the translating means and to the second real address storing means, for comparing the third real address to the second real address and for enabling the communication of a data word in the line register to the word receiving means when the third real address matches the second real address.
Claim 11
Dependent Claim
33 words
The cache memory system according to claim 9 wherein the second real address comprises a portion of the main memory starting address for the plurality of data words in the line of data.
Claim 12
Dependent Claim
32 words
The cache memory system according to claim 10 wherein the line communicating means communicates the plurality of data words in the addressed line of data in parallel to the line receiving means.
Claim 13
Dependent Claim
17 words
The cache memory system according to claim 11 wherein each line of data comprises four data words.
Claim 14
Dependent Claim
255 words
A cache memory system comprising: an addressable cache memory, including means for storing a plurality of lines of a plurality of data words, each data word having a main memory address associated therewith, the main memory addresses of the plurality of data words defining a boundary; first address receiving means, coupled to the cache memory, for receiving a first address from a CPU comprising a first real address portion and a virtual address portion and for addressing a line of data in the cache memory with the first real address portion of the first address; a line register, coupled to the cache memory, for independently storing the plurality of data words from a line of data in the cache memory; line communicating means, coupled to the cache memory and to the line register, for communicating the addressed line of data to the line register; word receiving means for receiving a data word stored in the line register; word communicating means, coupled to the line register and to the word receiving means, for selectively communicating a data word stored in the line register to the word receiving means; and boundary detecting means, coupled to the first address receiving means and to the word communicating means, for detecting whether the first address corresponds to a main memory address within the boundary and for enabling the communication of one of the plurality of data words stored in the line register to the word receiving means when the first address corresponds to a main memory address within the boundary.
Claim 15
Dependent Claim
255 words
A cache memory system comprising: an addressable cache memory, including means for storing a plurality of lines of a plurality of data words, each data word having a main memory address associated therewith, the main memory addresses of the plurality of data words defining a boundary; first address receiving means, coupled to the cache memory, for receiving a first address from a CPU comprising a first real address portion and a virtual address portion and for addressing a line of data in the cache memory with the first real address portion of the first address; a line register, coupled to the cache memory, for independently storing the plurality of data words from a line of data in the cache memory; line communicating means, coupled to the cache memory and to the line register, for communicating the addressed line of data to the line register; word receiving means for receiving a data word stored in the line register; word communicating means, coupled to the line register and to the word receiving means, for selectively communicating a data word stored in the line register to the word receiving means; and boundary detecting means, coupled to the first address receiving means and to the word communicating means, for detecting whether the first address corresponds to a main memory address within the boundary and for enabling the communication of one of the plurality of data words stored in the line register to the word receiving means when the first address corresponds to a main memory address within the boundary.
Claim 16
Dependent Claim
28 words
The cache memory system according to claim 13 wherein the plurality of data words in each line of data are from contiguous sequential addresses in a main memory.
Claim 17
Dependent Claim
58 words
The cache memory system according to claim 14 wherein the boundary detecting means comprises: a boundary register for storing a starting address of the plurality of data words in a line of data; and a boundary comparator, coupled to the boundary register and to the first address receiving means, for comparing the first address to the starting address.
Claim 18
Dependent Claim
50 words
The cache memory system according to claim 15 wherein the line communicating means is coupled to the boundary detecting means and communicates a next line of data in the cache memory to the line register when the first address does not correspond to a main memory address within the boundary.
Claim 19
Dependent Claim
36 words
The cache memory system according to claim 16 wherein the cache memory further comprises: second real address storing means for storing a second real address associated with the plurality of words of data of each line.
Claim 20
Dependent Claim
69 words
The cache memory system according to claim 17 further comprising: translation means, coupled to the first address receiving means and to the word communicating means, for storing a plurality of lines of address information, each line corresponding to a line of data in the cache memory, each line storing a third real address corresponding to the first address, the third real address being communicated to the word communicating means.
Claim 21
Dependent Claim
63 words
The cache memory according to claim 18 wherein the word communicating means further comprises: comparing means, coupled to the translating means and to the second real address storing means, for comparing the third real address to the second real address and for enabling the communication of the data word to the word register when the third real address matches the second real address.
Claim 22
Dependent Claim
32 words
The cache memory system according to claim 19 wherein the second real address comprises a portion of the main memory starting address for the plurality data words in the line of data.
Claim 23
Dependent Claim
33 words
The cache memory system according to claim 20 wherein the word communicating means uses a portion of the first address to select the data word to be communicated to the word receiving means.
Claim 24
Dependent Claim
31 words
The cache memory system according to claim 21 wherein the line communicating means communicates the plurality of data words in the line of data in parallel to the line receiving means.
Claim 25
Dependent Claim
17 words
The cache memory system according to claim 22 wherein each line of data comprises four data words.
Claim 26
Dependent Claim
416 words
A cache memory system comprising: an addressable cache memory, including means for storing a plurality of lines of a plurality of data words, each data word having a main memory address associated therewith, the main memory addresses of the plurality of data words defining a boundary, the cache memory including second real address storing means for storing a second real address associated with the plurality of data words of each line; first address receiving means, coupled to the cache memory, for receiving a first address from a CPU comprising a first real address portion and a virtual address portion and for addressing a line of data in the cache memory with the first real address; a line register, coupled to the cache memory, for receiving the plurality of data words from a line of data in the cache memory; line communicating means, coupled to the cache memory and to the line register, for communicating the data words in the addressed line of data to the line register; word receiving means for receiving a data word stored in the line register; word communicating means, coupled to the line register and to the word receiving means, for selectively communicating a data word stored in the line register to the word receiving means, the word communicating means comprising: translation means, coupled to the first address receiving means, for storing a plurality of lines of address information, each line corresponding to a line of data in the cache memory, each line in the translation means storing a third real address corresponding to the first address, for translating the first address to the third real address; comparing means, coupled to the translation means and to the second address storing means, for comparing the third real address to the second real address associated with the addressed line of data in the cache memory and for providing a first signal for enabling the communication of a data word stored in the line register to the word receiving means; and boundary detecting means, coupled to the first address receiving means, for detecting whether the virtual address portion of the first address corresponds to a main memory address within the boundary and for providing a second signal for enabling the communication of one of the plurality of data words stored in the line register to the word receiving means, independently of the translation of the first address to the third real address, when the first address corresponds to a main memory address within the boundary.
Claim 27
Dependent Claim
416 words
A cache memory system comprising: an addressable cache memory, including means for storing a plurality of lines of a plurality of data words, each data word having a main memory address associated therewith, the main memory addresses of the plurality of data words defining a boundary, the cache memory including second real address storing means for storing a second real address associated with the plurality of data words of each line; first address receiving means, coupled to the cache memory, for receiving a first address from a CPU comprising a first real address portion and a virtual address portion and for addressing a line of data in the cache memory with the first real address; a line register, coupled to the cache memory, for receiving the plurality of data words from a line of data in the cache memory; line communicating means, coupled to the cache memory and to the line register, for communicating the data words in the addressed line of data to the line register; word receiving means for receiving a data word stored in the line register; word communicating means, coupled to the line register and to the word receiving means, for selectively communicating a data word stored in the line register to the word receiving means, the word communicating means comprising: translation means, coupled to the first address receiving means, for storing a plurality of lines of address information, each line corresponding to a line of data in the cache memory, each line in the translation means storing a third real address corresponding to the first address, for translating the first address to the third real address; comparing means, coupled to the translation means and to the second address storing means, for comparing the third real address to the second real address associated with the addressed line of data in the cache memory and for providing a first signal for enabling the communication of a data word stored in the line register to the word receiving means; and boundary detecting means, coupled to the first address receiving means, for detecting whether the virtual address portion of the first address corresponds to a main memory address within the boundary and for providing a second signal for enabling the communication of one of the plurality of data words stored in the line register to the word receiving means, independently of the translation of the first address to the third real address, when the first address corresponds to a main memory address within the boundary.
Claim 28
Dependent Claim
28 words
The cache memory system according to claim 24 wherein the plurality of data words in each line of data are from contiguous sequential addresses in a main memory.
Claim 29
Dependent Claim
57 words
The cache memory system according to claim 25 wherein the boundary detecting means comprises: a boundary register for storing a starting address of the plurality of data words in the line register; and a boundary comparator, coupled to the boundary register and to the first address receiving means, for comparing the first address to the starting address.
Claim 30
Dependent Claim
36 words
The cache memory system according to claim 26 wherein the boundary detecting means detects whether the first address corresponds to a preselected one of the main memory addresses of the data words in the line register.
Claim 31
Dependent Claim
47 words
The cache memory system according to claim 27 wherein the line communicating means is coupled to the boundary detecting means and communicates a next sequential line of data in the cache memory to the line register when the first address corresponds to the preselected main memory address.
Claim 32
Dependent Claim
34 words
The cache memory system according to claim 28 wherein the second real address comprises a portion of the main memory starting address for the plurality of words of data in the line of data.
Claim 33
Dependent Claim
35 words
The cache memory system according to claim 29 wherein the word communicating means uses a portion of the first real address portion to select the data word to be communicated to the word receiving means.
Claim 34
Dependent Claim
30 words
The cache memory system according to claim 30 wherein the line communicating means communicates the plurality of words of data in the line in parallel to the line receiving means.
Claim 35
Dependent Claim
17 words
The cache memory system according to claim 31 wherein each line of data comprises four data words.
Claim 36
Dependent Claim
28 words
The cache memory system according to claim 32 wherein the main memory address of the first data word in each line of data is on a quadword boundary.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-21 | 1993-02-20 | 1993-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-21 | 1997-02-20 | 1997-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-21 | 2001-02-20 | 2001-08-22 | $7700.00 | Window Closed / Lapsed |