Patent US5318436A successfully refreshed from Google Patents.
Patent US4744084A successfully refreshed from Google Patents.
US4744084A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hardware modeling system and method for simulating portions of electrical circuits
Assignee: Mentor Graphics Corp
•
Filing: 1987-07-08
•
Granted: 1988-05-10
•
Expires: 2007-07-08
Abstract
Abstract A hardware modeling system 10 simulates portions of electrical circuits 16, 18 utilizing actual hardware components in the simulation. Access to these hardware modeling elements 16, 18 is provided on a shared basis to plural workstations 14. Simulation vectors for plural users may be stored discontiguously in a first memory 26 and a single user's vectors are transferred to a second memory 28 for streaming to the elements 16, 18. An optional timing analyzer and memory circuit 34 periodically samples outputs from pins of the hardware modeling elements to provide timing information on the response of such elements. High impedance testing and bus contention detection is performed on the pins of the hardware modeling elements. Clocking signals applied to the hardware modeling elements are adjustable and may be set at extremely high frequencies. A special gating circuit 292 accesses each pin of the hardware modeling elements and incorporates one or more of the above features.
Inventors
- 👤 Ronald R. Beck
- 👤 Michael E. Stanbro
- 👤 Eric J. Thomsen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:54
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
352 words
In a simulation system which includes plural workstations for independently and simultaneously simulating the response of electronic circuits to applied test data, a hardware modeling system for simulating the response of a plural pin circuit element by evaluating the behavior of an actual circuit element upon recognition by a workstation that the circuit element in an electronic circuit being simulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the hardware modeling system comprising: hardware modeling circuit means including input means for receiving input test data from the workstation, stimulus signal generation means coupled to the input means for converting the input test data into evaluation stimuli corresponding to the input test data, application means coupled to the stimulus signal generation means for applying the evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled coupled to the actual circuit element for receiving output signals from the actual circuit element and for converting the output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli, and output means coupled to the retrieval means for receiving the resultant test data; and network interface means for coupling the plural workstations to the hardware modeling circuit means so as to provide concurrent access by each of the workstations to the hardware modeling circuit means, said network interface means comprising means for coupling the workstations to the input means and for transferring input test data from a workstation to the input means upon recognition that the plural pin circuit element being stimulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the network interface means also comprising means coupling the output means to the workstations and for transfering resultant test data from the output means to the workstation following completion of a simulation, the network interface means thereby comprising means for interfacing the workstations to the hardware modeling circuit means so as to permit sharing of the hardware modeling circuit means among the workstations for concurrent circuit simulations by the workstations.
Claim 2
Dependent Claim
352 words
In a simulation system which includes plural workstations for independently and simultaneously simulating the response of electronic circuits to applied test data, a hardware modeling system for simulating the response of a plural pin circuit element by evaluating the behavior of an actual circuit element upon recognition by a workstation that the circuit element in an electronic circuit being simulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the hardware modeling system comprising: hardware modeling circuit means including input means for receiving input test data from the workstation, stimulus signal generation means coupled to the input means for converting the input test data into evaluation stimuli corresponding to the input test data, application means coupled to the stimulus signal generation means for applying the evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled coupled to the actual circuit element for receiving output signals from the actual circuit element and for converting the output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli, and output means coupled to the retrieval means for receiving the resultant test data; and network interface means for coupling the plural workstations to the hardware modeling circuit means so as to provide concurrent access by each of the workstations to the hardware modeling circuit means, said network interface means comprising means for coupling the workstations to the input means and for transferring input test data from a workstation to the input means upon recognition that the plural pin circuit element being stimulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the network interface means also comprising means coupling the output means to the workstations and for transfering resultant test data from the output means to the workstation following completion of a simulation, the network interface means thereby comprising means for interfacing the workstations to the hardware modeling circuit means so as to permit sharing of the hardware modeling circuit means among the workstations for concurrent circuit simulations by the workstations.
Claim 3
Dependent Claim
46 words
A simulation system according to claim 1 including plural hardware modeling circuit means, said network interface means comprising means for interfacing the workstations to such plural hardware modeling circuit means so as to permit sharing of the plural hardware modeling circuit means among the plural workstations.
Claim 4
Dependent Claim
119 words
A system according to claim 1 in which the hardware modeling circuit means includes plural integrated circuit interface means and input/output port means for coupling to actual circuit elements, the integrated circuit interface means and input/output port means including the stimulus signal generation means coupled to the input means for receiving input test data and for generating evaluation stimuli corresponding to the input test data, the application means coupled to the stimulus signal generation means for applying evaluation stimuli to the actual circuit elements, and the retrieval means coupled to the actual circuit elements for receiving output signals from the actual circuit elements, the output signals being generated by the actual circuit elements in response to the evaluation stimuli.
Claim 5
Dependent Claim
108 words
The hardware modeling system of claim 1 in which the input means comprises: a first semiconductor memory circuit capable of operating at a first rate for storing input test data for use in a plurality of simulations; a second semiconductor memory circuit capable of operating at a second rate faster than the first rate for storing input test data for use in a single simulation; means for transferring input test data for use in a single simulation from the first semiconductor memory circuit to the second semiconductor memory circuit; and means for transferring input test data from the second semiconductor memory circuit to the stimulus signal generation means.
Claim 6
Dependent Claim
125 words
A hardware modeling system with a plurality of different plural pin hardware modeling elements used for performing simulations of the performance of electronic circuits in response to input test data, means for converting test data to evaluation stimuli and for applying the evaluation stimuli to selected input pins of the hardware modeling element, means for retrieving output signals from selected output pins of the hardware modeling element and for converting the output signals to resultant test data, timing analyzer circuit means for periodically sampling the resultant data from the output pins to provide a timing representation of the resultant data at the output pins over time, and means for selectively coupling the timing analyzer circuit means to the output pins to provide the timing representation.
Claim 7
Dependent Claim
125 words
A hardware modeling system with a plurality of different plural pin hardware modeling elements used for performing simulations of the performance of electronic circuits in response to input test data, means for converting test data to evaluation stimuli and for applying the evaluation stimuli to selected input pins of the hardware modeling element, means for retrieving output signals from selected output pins of the hardware modeling element and for converting the output signals to resultant test data, timing analyzer circuit means for periodically sampling the resultant data from the output pins to provide a timing representation of the resultant data at the output pins over time, and means for selectively coupling the timing analyzer circuit means to the output pins to provide the timing representation.
Claim 8
Dependent Claim
99 words
A hardware modeling system according to claim 5 including: user memory means for storing input test data for one or more simulations; operating memory means for storing input test data for only one simulation; means for applying input test data from the operating memory means to said means for converting test data during a simulation; and means for transferring input test data for a single simulation from the user memory means to the operatin memory means following the application of input test data for a prior simulation from the operating memory means to the means for converting test data.
Claim 9
Dependent Claim
178 words
In a hardware modeling system in which evaluation stimuli corresponding to data signals and clocking signals are applied to pins of a plurality of different plural pin hardware modeling elements used in circuit simulations so as to produce output signals from output pins of the hardware modeling elements and thereby simulation results; gating circuit means with plural circuit pin connections, each such pin connection for connection to a single associated pin of a hardware modeling element; means for selecting any of the pin connections as input data pin connections; means for transferring test stimuli to the input data pin connections and thereby to the associated pins of the hardware modeling element; means for selecting any of the pin connections as clock pin connections; means for transferring clocking signals to the clock pin connections and thereby to the associated pins of the hardware modeling element; means for selecting any of the pin connections as output data connections; and means for receiving output data from the output data connections and thereby from the associated pins of the hardware modeling element.
Claim 10
Dependent Claim
178 words
In a hardware modeling system in which evaluation stimuli corresponding to data signals and clocking signals are applied to pins of a plurality of different plural pin hardware modeling elements used in circuit simulations so as to produce output signals from output pins of the hardware modeling elements and thereby simulation results; gating circuit means with plural circuit pin connections, each such pin connection for connection to a single associated pin of a hardware modeling element; means for selecting any of the pin connections as input data pin connections; means for transferring test stimuli to the input data pin connections and thereby to the associated pins of the hardware modeling element; means for selecting any of the pin connections as clock pin connections; means for transferring clocking signals to the clock pin connections and thereby to the associated pins of the hardware modeling element; means for selecting any of the pin connections as output data connections; and means for receiving output data from the output data connections and thereby from the associated pins of the hardware modeling element.
Claim 11
Dependent Claim
33 words
A gating circuit according to claim 7 including means for selectively applying a variable logic 0, logic 1 or high impedance to any of the pin connections and thereby to the associated pins.
Claim 12
Dependent Claim
30 words
A gating circuit according to claim 7 including means for selectively applying a pull-up or a pull-down load to any of the pin connections and thereby to the associated pins.
Claim 13
Dependent Claim
43 words
A hardware modeling system according to claim 7 which includes means for selectively applying clock signals to any of the pins of the actual circuit element, and also includes means for adjusting the phase, duty cycle and frequency of the applied clock signals.
Claim 14
Dependent Claim
248 words
A hardware modeling system in which evaluation stimuli corresponding to data signals and clocking signals are applied to pins of a plural pin hardware modeling element corresponding to a component in a circuit being simulated so as to produce output signals from output pins of the hardware modeling element for use in the circuit stimulation, the system including; gating circuit means with plural circuit pin connections, each such pin connection for connection to a single associated pin of a hardware modeling element; means for selecting any of the pin connections as input data pin connections; means for transferring test stimuli to the input data pin connections and thereby to the associated pins of the hardware modeling element; means for selecting any of the pin connections as clock pin connections; means for transferring clocking signals to the clock pin connections and thereby to the associated pins of the hardware modeling element; means for selecting any of the pin connections as output data connections; means for receiving output data from the output data connections and thereby from the associated pins of the hardware modeling element; the system further including bus contention detection means for indicating when any of such pin connections are driven by a signal from a hardware modeling element to one state while the same pin connection is driven by a signal from the gating circuit to an opposite state, and for disabling at least one of the drive signals applied to the pin connection under such conditions.
Claim 15
Dependent Claim
248 words
A hardware modeling system in which evaluation stimuli corresponding to data signals and clocking signals are applied to pins of a plural pin hardware modeling element corresponding to a component in a circuit being simulated so as to produce output signals from output pins of the hardware modeling element for use in the circuit stimulation, the system including; gating circuit means with plural circuit pin connections, each such pin connection for connection to a single associated pin of a hardware modeling element; means for selecting any of the pin connections as input data pin connections; means for transferring test stimuli to the input data pin connections and thereby to the associated pins of the hardware modeling element; means for selecting any of the pin connections as clock pin connections; means for transferring clocking signals to the clock pin connections and thereby to the associated pins of the hardware modeling element; means for selecting any of the pin connections as output data connections; means for receiving output data from the output data connections and thereby from the associated pins of the hardware modeling element; the system further including bus contention detection means for indicating when any of such pin connections are driven by a signal from a hardware modeling element to one state while the same pin connection is driven by a signal from the gating circuit to an opposite state, and for disabling at least one of the drive signals applied to the pin connection under such conditions.
Claim 16
Dependent Claim
29 words
An apparatus according to claim 11 including timing analyzer means selectively coupled to the output pin connections for performing timing analysis on output signals received from the associated pins.
Claim 17
Dependent Claim
41 words
An apparatus according to claim 11 including clocking means for applying clocking signals to the clocking pin connections, such clocking means including means for varying the frequency, duty cycle and phase of clocking signals applied to each such clocking pin connection.
Claim 18
Dependent Claim
385 words
A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising: memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli; the memory means comprising means coupled to the resultant test data retriveval means for receiving and storing the resultant test data; control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli to the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation; and the memory means including first memory means for receiving and storing input test data from the workstation for plural circuit simulations, second memory means for receiving input test data from the first memory means for a single simulation, the control circuit means comprising means for controlling the transfer of input test data for a simulation from the second memory means to the circuit interface means and for controlling the transfer of input test data for a single simulation from the first memory means to the second memory means following the transfer from the second memory means to the circuit interface means.
Claim 19
Dependent Claim
385 words
A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising: memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli; the memory means comprising means coupled to the resultant test data retriveval means for receiving and storing the resultant test data; control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli to the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation; and the memory means including first memory means for receiving and storing input test data from the workstation for plural circuit simulations, second memory means for receiving input test data from the first memory means for a single simulation, the control circuit means comprising means for controlling the transfer of input test data for a simulation from the second memory means to the circuit interface means and for controlling the transfer of input test data for a single simulation from the first memory means to the second memory means following the transfer from the second memory means to the circuit interface means.
Claim 20
Dependent Claim
35 words
A hardware modeling system according to claim 14 which the control circuit means comprises means for controlling the transfer of resultant test data from the resultant test data retrieval means to the first memory means.
Claim 21
Dependent Claim
19 words
The hardware modeling system of claim 14 in which the first and second memory means comprise semiconductor memory circuits.
Claim 22
Dependent Claim
22 words
The hardware modeling system of claim 16 in which the second semiconductor memory circuit can be accessed more quickly than the first.
Claim 23
Dependent Claim
32 words
A system according to claim 14 in which the first memory means operates at a first rate and the second memory means operates at a second rate greater than the first rate.
Claim 24
Dependent Claim
62 words
A hardware modeling system according to claim 14 in which the control cirucit means includes device clock means for generating device clock signals for clocking the actual circuit elements, the control circuit means also including means for selectively positioning the rising and falling edges of the device clock signals relative to the evaluation stimuli and thus relative to the input test data.
Claim 25
Dependent Claim
29 words
A system according to claim 14 in which the second memory means has a full pattern depth available to each circuit element during a simulation using the circuit element.
Claim 26
Dependent Claim
427 words
A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising: memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli; the memory means comprising means coupled to the resultant test data retrieval means for receiving and storing the resultant test data; control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli to the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation; the memory means including first memory means for receiving and storing input test data from the workstation for plural circuit simulations, second memory means for receiving input test data from the first memory means for a single simulation, the control circuit means comprising means for controlling the transfer of input test data for a simulation from the second memory means to the circuit interface means and for controlling the transfer of input test data for a single simulation from the first memory means to the second memory means following the transfer from the second memory means to the circuit interface means; and the memory means including third supplemental disk memory means which acts as a virtual memory means, the hardware modeling system including means for swapping inputting test data from the first to third memory means and from the third to first memory means.
Claim 27
Dependent Claim
427 words
A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising: memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli; the memory means comprising means coupled to the resultant test data retrieval means for receiving and storing the resultant test data; control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli to the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation; the memory means including first memory means for receiving and storing input test data from the workstation for plural circuit simulations, second memory means for receiving input test data from the first memory means for a single simulation, the control circuit means comprising means for controlling the transfer of input test data for a simulation from the second memory means to the circuit interface means and for controlling the transfer of input test data for a single simulation from the first memory means to the second memory means following the transfer from the second memory means to the circuit interface means; and the memory means including third supplemental disk memory means which acts as a virtual memory means, the hardware modeling system including means for swapping inputting test data from the first to third memory means and from the third to first memory means.
Claim 28
Dependent Claim
60 words
A hardware modeling system according to claim 16 including timing analyzer and memory circuit means coupled to the resultant test data retrieval means for selectively receiving resultant test data, the control circuit means comprising means for periodically transferring resultant test data to the timing analyzer and memory circuit means to provide a representation of such resultant test data over time.
Claim 29
Dependent Claim
43 words
A hardware modeling system according to claim 22 in which the control circuit means includes means for applying timing analysis clocking signals to the timing analyzer and memory circuit means to transfer resultant test data in response to the timing analysis clocking signals.
Claim 30
Dependent Claim
71 words
A hardware modeling system according to claim 21 including high impedance testing means for determining whether a pin of the actual circuit element is at a high impedance state, the high impedance testing means comprising means for applying a logic high signal and a logic low signal to the pin and evaluating whether the pin is pulled to the logic high and logic low states in response to the applied signals.
Claim 31
Dependent Claim
32 words
A system according to claim 21 in which the first memory means operates at a first rate and the second memory means operates at a second rate greater than the first rate.
Claim 32
Dependent Claim
394 words
A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising: memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli; the memory means comprising means coupled to the resultant test data retrieval means for receiving and storing the resultant test data; control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli by the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation; the control circuit means including first clock means for clocking a first set of input test data from the memory means to the circuit interface means, second clock means for clocking a second set of input test data from the memory means to the circuit interface means, master clock means for generating master clock signals for clocking the stimulus signal generation means following the transfers of the first and second sets of input test data, thereby controlling the generation of evaluation stimuli to correspond to both of the first and second sets of input test data, and device clock means for generating device clock signals for clocking the actual circuit elements.
Claim 33
Dependent Claim
394 words
A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising: memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli; the memory means comprising means coupled to the resultant test data retrieval means for receiving and storing the resultant test data; control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli by the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation; the control circuit means including first clock means for clocking a first set of input test data from the memory means to the circuit interface means, second clock means for clocking a second set of input test data from the memory means to the circuit interface means, master clock means for generating master clock signals for clocking the stimulus signal generation means following the transfers of the first and second sets of input test data, thereby controlling the generation of evaluation stimuli to correspond to both of the first and second sets of input test data, and device clock means for generating device clock signals for clocking the actual circuit elements.
Claim 34
Dependent Claim
35 words
The hardware modeling system according to claim 26 in which the control circuit means includes means for selectively positioning the rising and falling edges of the device clock signals relative to the master clock signals.
Claim 35
Dependent Claim
341 words
A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising: memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli; the memory means comprising means coupled to the resultant test data retreval means for receiving and storing the resultant test data; control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli by the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation; the system further including bus contention means for detcting bus contentions, a bus contention occurring upon the application of a drive signal by the application means to a pin of the actual circuit element simultaneously with the generation of an output drive signal at such pin by the actual circuit element in response to the applied evaluation stimuli.
Claim 36
Dependent Claim
341 words
A hardware modeling system for simulating the response of at least one plural pin circuit element in an electronic circuit being simulated at a workstation by evaluating the behavior of an actual plural pin circuit element in response to test data from the workstation, comprising: memory means for receiving and storing input test data from the workstation; circuit interface means for coupling to the actual circuit element, the circuit interface means being coupled to the memory means for receiving the input test data from the memory means, the interface means comprising stimulus signal generation means for generating evaluation stimuli corresponding to the input test data, application means for applying evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and converting the received output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli; the memory means comprising means coupled to the resultant test data retreval means for receiving and storing the resultant test data; control circuit means coupled to the memory means and to the circuit interface means for controlling the transfer of input test data from the memory means to the circuit interface means, for controlling the application of the evaluation stimuli by the actual circuit element by the application means, for controlling the receiving of output signals and conversion of output signals to resultant test data by the resultant test data retrieval means, and for controlling the transfer of resultant test data to the memory means and the return of the resultant test data from the memory means to the workstation; the system further including bus contention means for detcting bus contentions, a bus contention occurring upon the application of a drive signal by the application means to a pin of the actual circuit element simultaneously with the generation of an output drive signal at such pin by the actual circuit element in response to the applied evaluation stimuli.
Claim 37
Dependent Claim
55 words
A hardware modeling system according to claim 28 in which the bus contention means includes means for changing the drive signal which is applied to such pin by the application means to a high-impedance signal upon detection of a bus contention at such pin to thereby minimize the risk of damage from the bus contention.
Claim 38
Dependent Claim
103 words
An electronic circuit simulation method in which actual plural pin hardware circuit elements are used in the simulation comprising: storing test data for plural simulations in a first memory; transferring test data for a single simulation from the first memory to a second memory; applying test data for the single simulation from the second memory to an actual hardware circuit element to provide resultant test data from the circuit element; and transferring test data for successive single simulations from the first memory to the second memory following the application of test data for a prior single simulation to an actual hardware modeling element.
Claim 39
Dependent Claim
103 words
An electronic circuit simulation method in which actual plural pin hardware circuit elements are used in the simulation comprising: storing test data for plural simulations in a first memory; transferring test data for a single simulation from the first memory to a second memory; applying test data for the single simulation from the second memory to an actual hardware circuit element to provide resultant test data from the circuit element; and transferring test data for successive single simulations from the first memory to the second memory following the application of test data for a prior single simulation to an actual hardware modeling element.
Claim 40
Dependent Claim
50 words
A method according to claim 30, including the step of sampling output signals from output pins of an actual circuit element as test data is applied to the actual circuit element during a simulation, thereby providing a representation of the output signals at the sampled output pins during the simulation.
Claim 41
Dependent Claim
49 words
A method according to claim 30 comprising the steps of transferring test data at a first rate from the first memory to the second memory and applying the test data at a second rate higher than the first rate from the second memory to the actual hardware circuit element.
Claim 42
Dependent Claim
438 words
In a simulation system which includes plural workstations for simulating the response of electronic circuits to applied test data, a hardware modeling system for simulating the response of at least one plural pin circuit element by evaluating the behavior of an actual circuit element upon recognition by a workstation that the circuit element in an electronic circuit being simulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the hardware modeling system comprising: hardware modeling circuit means including input means for receiving input test data from the workstations, stimulus signal generation means coupled to the input means for converting the input test data into evaluation stimuli corresponding to the input test data, application means coupled to the stimulus signal generation means for applying the evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and for converting the output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli, and output means coupled to the retrieval means for receiving the resultant test data; network interface means for coupling the plural workstations to the hardware modeling circuit means so as to provide access by each of the workstations to the hardware modeling circuit means, said network interface means comprising means for coupling the workstations to the input means and for transferring input test data from a workstation to the input means upon recognition that the plural pin circuit element being stimulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the network interface means also comprising means coupling the output means to the workstations and for transferring resultant test data from the output means to the workstation following completion of a simulation, the network interface means thereby comprising means for interfacing the workstations to the hardware modeling circuit means so as to permit sharing of the hardware modeling circuit means among the workstations; and the hardware modeling circuit means including: user memory means for storing input test data for one or more simulations; operating memory means for storing input test data for only one simulation; means for applying input test data from the operating memory means to said means for converting test data during a simulation; and means for transferring input test data for a single simulation from the user memory means to the operating memory means following the application of input test data for a prior simulation from the operating memory means to the means for converting test data.
Claim 43
Dependent Claim
438 words
In a simulation system which includes plural workstations for simulating the response of electronic circuits to applied test data, a hardware modeling system for simulating the response of at least one plural pin circuit element by evaluating the behavior of an actual circuit element upon recognition by a workstation that the circuit element in an electronic circuit being simulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the hardware modeling system comprising: hardware modeling circuit means including input means for receiving input test data from the workstations, stimulus signal generation means coupled to the input means for converting the input test data into evaluation stimuli corresponding to the input test data, application means coupled to the stimulus signal generation means for applying the evaluation stimuli to the actual circuit element, resultant test data retrieval means coupled to the actual circuit element for receiving output signals from the actual circuit element and for converting the output signals to resultant test data, the output signals being generated by the actual circuit element in response to the applied evaluation stimuli, and output means coupled to the retrieval means for receiving the resultant test data; network interface means for coupling the plural workstations to the hardware modeling circuit means so as to provide access by each of the workstations to the hardware modeling circuit means, said network interface means comprising means for coupling the workstations to the input means and for transferring input test data from a workstation to the input means upon recognition that the plural pin circuit element being stimulated at the workstation corresponds to an actual circuit element in the hardware modeling system, the network interface means also comprising means coupling the output means to the workstations and for transferring resultant test data from the output means to the workstation following completion of a simulation, the network interface means thereby comprising means for interfacing the workstations to the hardware modeling circuit means so as to permit sharing of the hardware modeling circuit means among the workstations; and the hardware modeling circuit means including: user memory means for storing input test data for one or more simulations; operating memory means for storing input test data for only one simulation; means for applying input test data from the operating memory means to said means for converting test data during a simulation; and means for transferring input test data for a single simulation from the user memory means to the operating memory means following the application of input test data for a prior simulation from the operating memory means to the means for converting test data.
Claim 44
Dependent Claim
70 words
A system according to claim 33 in which the means for transferring input test data from the user memory means to the operating memory means comprises means for transferring such input test data at a first rate, and in which the means for applying input test data from the operating memory means comprises means for applying such test data at a second rate which is greater than the first rate.
Claim 45
Dependent Claim
29 words
A system according to claim 34 in which the operating memory means has a full pattern depth available to each circuit element during a simulation using the circuit element.
Claim 46
Dependent Claim
56 words
A system according to claim 33 including third supplemental disk memory means which acts as a virtual memory means, the hardware modeling circuit means including means for swapping input test data from the first to third memory means and from the third to first memory means as the first memory means fills with input test data.
Claim 47
Dependent Claim
110 words
A simulation system comprising: plural workstations each capable of independently performing circuit evaluations of various circuit in which the evaluations involve at least in part a software simulation of the circuit being evaluated by each workstation; hardware modeling circuit means coupled to the plural workstations and including at least one actual circuit element, the hardware modeling circuit means comprising means for providing shared access by the plural workstations to the actual circuit element, the hardware modeling circuit means comprsing means permitting the plural workstations to perform concurrent circuit evaluations using the actual hardware element in the evaluation when such element appears in the circuits being evaluated by the plural workstations.
Claim 48
Dependent Claim
110 words
A simulation system comprising: plural workstations each capable of independently performing circuit evaluations of various circuit in which the evaluations involve at least in part a software simulation of the circuit being evaluated by each workstation; hardware modeling circuit means coupled to the plural workstations and including at least one actual circuit element, the hardware modeling circuit means comprising means for providing shared access by the plural workstations to the actual circuit element, the hardware modeling circuit means comprsing means permitting the plural workstations to perform concurrent circuit evaluations using the actual hardware element in the evaluation when such element appears in the circuits being evaluated by the plural workstations.
Claim 49
Dependent Claim
19 words
A simulation system according to claim 37 in which the hardware modelling circuit means has plural actual circuit elements.
References Cited (Backward Citations)
US31056A
Cited
US930005A
Cited
US3643156A
Cited
US3603936A
Cited
US3673397A
Cited
US3715573A
Cited
US3739349A
Cited
US3758761A
Cited
JPS4837581A
Cited
US3872441A
Cited
US3764995A
Cited
US3777129A
Cited
UST930005I4
Cited
US3832535A
Cited
US3932843A
Cited
US3812337A
Cited
US3927371A
Cited
US4031517A
Cited
US4000460A
Cited
JPS5172251A
Cited
JPS5176047A
Cited
JPS5185344A
Cited
JPS51113336A
Cited
US4300196A
Cited
US4044244A
Cited
US4066882A
Cited
US4070565A
Cited
US4196475A
Cited
US4130283A
Cited
JPS5388547A
Cited
USRE31056E
Cited
JPS53119642A
Cited
JPS543443A
Cited
US4213175A
Cited
US4180023A
Cited
JPS5431863A
Cited
JPS5454541A
Cited
JPS5456335A
Cited
US4156132A
Cited
JPS5475251A
Cited
JPS54111241A
Cited
JPS54122053A
Cited
US4216533A
Cited
US4213253A
Cited
US4242751A
Cited
US4228537A
Cited
JPS5537602A
Cited
JPS5556261A
Cited
US4317200A
Cited
JPS5557955A
Cited
US4236246A
Cited
DE2848621A1
Cited
US4456994A
Cited
JPS55108054A
Cited
JPS55107964A
Cited
US4310884A
Cited
US4404627A
Cited
JPS55153054A
Cited
US4342093A
Cited
JPS55157039A
Cited
JPS55157045A
Cited
US4306286A
Cited
US4348759A
Cited
US4370728A
Cited
US4354268A
Cited
US4500993A
Cited
US4484329A
Cited
US4357703A
Cited
US4402055A
Cited
US4404635A
Cited
US4488299A
Cited
US4397021A
Cited
US4517661A
Cited
US4451918A
Cited
US4450560A
Cited
US4493045A
Cited
US4555756A
Cited
US4488354A
Cited
US4510572A
Cited
US4495642A
Cited
US4513384A
Cited
US4527234A
Cited
US4620304A
Cited
GB2131211A
Cited
US4527249A
Cited
US4607366A
Cited
US4613940A
Cited
US4500963A
Cited
US4544882A
Cited
US4644487A
Cited
US4604718A
Cited
EP0129017A2
Cited
US4590581B1
Cited
US4635218A
Cited
US4590581A
Cited
US4587625A
Cited
US4635256A
Cited
US4638481A
Cited
US4656632A
Cited
EP0150258A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-10 | 1991-11-09 | 1992-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-10 | 1995-11-09 | 1996-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-10 | 1999-11-09 | 2000-05-10 | $7700.00 | Window Closed / Lapsed |