Timing analyzer with combination transition and duration trigger

Claim 2

A logic timing analyzer or the like, comprising: signal acquisition means for receiving a collection of fluctuating input data signals to be compared against logical thresholds and for producing from the fluctuating input data signals a corresponding collection of acquired signals; pattern recognition means coupled to the collection of acquired signals for causing a recognition signal to appear for any duration that the collection of acquired signals matches a preselected pattern and for causing the recognition signal to disappear for any duration that the collection of acquired signals differs from the preselected pattern; trigger signal generation means coupled to the recognition signal for producing a trigger signal when the duration between an appearance of the recognition signal and a subsequent disappearance thereof is less than a preselected duration; a data acquisition memory, coupled to the collection of acquired signals and the trigger signal, and responsive to the trigger signal by ceasing to store the collection of acquired signals after a predetermined amount of time subsequent to the occurrence of the trigger signal; and display means coupled to the data acquisition memory for displaying the contents thereof.

Claim 3

A trigger signal qualification circuit for timing analyzers and the like, comprising: a pattern recognition circuit responsive to input data signals by producing a recognition signal wherever the input data signals match a preselected pattern; selective inversion means coupled to the recognition signal for producing a trigger signal that represents a preselected logical sense of the recognition signal; transition detection means coupled to the trigger signal for detecting transitions therein from a first logical sense to a second logical sense and for producing a transition signal indicative thereof; time duration comparison means coupled to the trigger signal for detecting transitions therein from the second logical sense to the first logical sense and also for producing a time-out signal indicative of whether the amount of time since the most recent transition in the trigger signal from the second logical sense to the first logical sense is both free from a subsequent transition from the first logical sense to the second logical sense and is greater than a preselected duration; logic means coupled to the transition signal and to the time-out signal for producing an output signal whenever the transition signal occurs while the the time-out signal is absent; and selection means coupled to receive as inputs the transition signal, the time-out signal and the output of the logic means, for producing a qualified trigger signal upon the occurrence of a preselected one of the input coupled to the selection means.

Claim 4

A trigger signal qualification circuit for timing analyzers and the like, comprising: a pattern recognition circuit responsive to input data signals by producing a recognition signal wherever the input data signals match a preselected pattern; selective inversion means coupled to the recognition signal for producing a trigger signal that represents a preselected logical sense of the recognition signal; transition detection means coupled to the trigger signal for detecting transitions therein from a first logical sense to a second logical sense and for producing a transition signal indicative thereof; time duration comparison means coupled to the trigger signal for detecting transitions therein from the second logical sense to the first logical sense and also for producing a time-out signal indicative of whether the amount of time since the most recent transition in the trigger signal from the second logical sense to the first logical sense is both free from a subsequent transition from the first logical sense to the second logical sense and is greater than a preselected duration; logic means coupled to the transition signal and to the time-out signal for producing an output signal whenever the transition signal occurs while the the time-out signal is absent; and selection means coupled to receive as inputs the transition signal, the time-out signal and the output of the logic means, for producing a qualified trigger signal upon the occurrence of a preselected one of the input coupled to the selection means.

Claim 5

A timing analyzer or the like incorporating the trigger signal qualification circuit of claim 2, further comprising: memory means coupled to the qualified trigger signal for storing samples of the input data signals and for responding to the qualified trigger signal by ceasing to store samples after a predetermined amount of time subsequent to the occurrence of the qualified trigger signal; and display means coupled to the memory means for displaying the contents thereof.

Claim 6

A combined qualified-trigger selection circuit for a timing analyzer or the like comprising a first trigger signal qualification circuit as in claim 2, the selection circuit further comprising: a second trigger signal qualification circuit as in claim 2; selection means coupled to first and second qualified trigger signals respectively produced by the first and second trigger signal qualification circuits for producing a doubly qualified trigger signal representing a preselected one of first and second conditions, the first condition being the logical conjunction of the first and second qualified trigger signals, and the second condition being the logical conjunction of the first qualified trigger signal and another signal indicating previous occurrence of the second qualified trigger signal.

Claim 7

A timing analyzer or the like incorporating the combined qualified-trigger selection circuit of claim 4, further comprising: memory means coupled to the doubly qualified trigger signal for storing samples of the input data signals and for responding to the doubly qualified trigger signal by ceasing to store samples after a predetermined amount of time subsequent to the occurrence of the doubly qualified trigger signal; and display means coupled to the memory means for displaying the contents thereof.