US4364036A
Expired / Lapsed
US
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Composite logic analyzer capable of data display in two time-related formats
Assignee: Iwatsu Electric Co Ltd
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Filing: 1980-11-24
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Granted: 1982-12-14
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Expires: 2000-11-24
Abstract
Abstract A combined logic timing and state analyzer comprises an internally clocked, timing analyzer section receiving a first set of logic signals, and an externally clocked, state analyzer section receiving a second set of logic signals. The timing analyzer section samples the first set of logic signals, as well as the external clock signal associated with the second set of logic signals, at a rate determined by the internal clock pulses and stores the samples in a first set of memories. The state analyzer section samples the second set of logic signals at a rate determined by the external clock pulses and stores the samples in a second set of memories. Data introduction into the memories terminates when they are triggered, as in the event of a malfunction of the system being investigated. The logic analyzer further includes a display circuit for repetitively reading out the first and the second sets of memories and for causing a display device to visually present the output data of the first memory set in the form of a timing diagram and the output data of the second memory set in the form of a state table. The time relationship between the two display formats can be readily ascertained since the timing diagram includes a waveform, or other visual representations, indicative of the external clock pulses used for sampling the second set of logic signals.
Inventors
- 👤 Kazunari Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:50
CPC Classifications
G; G01; G01R; G01R13/00; G01R13/20; G01R13/22; G01R31/00; G01R31/28; G01R31/317; G01R31/3177; G06; G06F; G06F11/00; G06F11/22; G06F11/25
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
368 words
A composite logic analyzer capable of displaying a first and a second set of data in different, time-related formats, comprising: (a) first input means for receiving a first set of logic signals; (b) second input means for receiving a second set of logic signals; (c) additional input means for receiving an external clock signal associated with the second set of logic signals; (d) an internal clock for generating an internal clock signal having a repetition frequency higher than that of the external clock signal; (e) first sampler means coupled to the first input means for sampling the first set of logic signals at a rate determined by the internal clock signal; (f) second sampler means coupled to the second input means for sampling the second set of logic signals at a rate determined by the external clock signal; (g) additional sampler means coupled to the additional input means for sampling the external clock signal at a rate determined by the internal clock signal; (h) first memory means coupled to the first sampler means for storing the samples of the first set of logic signals under the control of the internal clock signal; (i) second memory means coupled to the second sampler means for storing the samples of the second set of logic signals under the control of the external clock signal; (j) additional memory means coupled to the additional sampler means for storing the samples of the external clock signal under the control of the internal clock signal; (k) trigger means coupled to the first, the second and the additional memory means for triggering same and hence for suspending the introduction of the samples therein; (l) a display circuit coupled to the first, the second and the additional memory means for producing a first set of display signals for displaying in a first format the data recovered from the first and the additional memory means, and for producing a second set of display signals for displaying in a second format the data recovered from the second memory means; and (m) a display device coupled to the display circuit for making visual presentation of the output data in response to the first and the second sets of display signals.
Claim 2
Dependent Claim
368 words
A composite logic analyzer capable of displaying a first and a second set of data in different, time-related formats, comprising: (a) first input means for receiving a first set of logic signals; (b) second input means for receiving a second set of logic signals; (c) additional input means for receiving an external clock signal associated with the second set of logic signals; (d) an internal clock for generating an internal clock signal having a repetition frequency higher than that of the external clock signal; (e) first sampler means coupled to the first input means for sampling the first set of logic signals at a rate determined by the internal clock signal; (f) second sampler means coupled to the second input means for sampling the second set of logic signals at a rate determined by the external clock signal; (g) additional sampler means coupled to the additional input means for sampling the external clock signal at a rate determined by the internal clock signal; (h) first memory means coupled to the first sampler means for storing the samples of the first set of logic signals under the control of the internal clock signal; (i) second memory means coupled to the second sampler means for storing the samples of the second set of logic signals under the control of the external clock signal; (j) additional memory means coupled to the additional sampler means for storing the samples of the external clock signal under the control of the internal clock signal; (k) trigger means coupled to the first, the second and the additional memory means for triggering same and hence for suspending the introduction of the samples therein; (l) a display circuit coupled to the first, the second and the additional memory means for producing a first set of display signals for displaying in a first format the data recovered from the first and the additional memory means, and for producing a second set of display signals for displaying in a second format the data recovered from the second memory means; and (m) a display device coupled to the display circuit for making visual presentation of the output data in response to the first and the second sets of display signals.
Claim 3
Dependent Claim
53 words
The composite logic analyzer as recited in claim 1, wherein: (a) the first set of logic signals are control signals from computer logic circuitry; (b) the second set of logic signals are bus signals from the computer logic circuitry; and (c) the external clock signal is a clock signal for the bus signals.
Claim 4
Dependent Claim
111 words
The composite logic analyzer as recited in claim 1, wherein the display circuit comprises: (a) a first display signal generator circuit coupled to the first and the additional memory means for producing vertical axis, horizontal axis, and luminance signals as the first set of display signals; (b) a second display signal generator circuit coupled to the second memory means for producing vertical axis, horizontal axis, and luminance signals as the second set of display signals; and (c) a selector switch circuit connected between the first and second display signal generator circuits and the display device for permitting the selective passage therethrough of the first and the second sets of display signals.
Claim 5
Dependent Claim
49 words
The composite logic analyzer as recited in claims 1 or 3, wherein: (a) the first set of display signals are for displaying the data in the form of a timing diagram; and (b) the second set of display signals are for displaying the data in the form of characters.
Claim 6
Dependent Claim
88 words
The composite logic analyzer as recited in claim 1, further comprising: (a) first wave-shaping means connected between the first input means and the first sampler means for shaping the waveforms of the first set of logic signals; (b) second wave-shaping means connected between the second input means and the second sampler means for shaping the waveforms of the second set of logic signals; and (c) additional wave-shaping means connected between the additional input means and the additional sampler means for shaping the waveform of the external clock signal.
Claim 7
Dependent Claim
52 words
The composite logic analyzer as recited in claim 1, wherein the trigger means comprises: (a) a first trigger generator; (b) a first delay circuit connected between the trigger generator and the first and additional memory means; and (c) a second delay circuit connected between the trigger generator and the second memory means.
Claim 8
Dependent Claim
44 words
The composite logic analyzer as recited in claim 1, further comprising: (a) second additional input means for receiving another first logic signal; and (b) a selector switch for selectively connecting the first recited and the second additional input means to the additional sampler means.
Claim 9
Dependent Claim
84 words
The composite logic analyzer as recited in claim 1, wherein the additional input means receives a plurality of external clock signals, and wherein the analyzer further comprises: (a) second additional input means for receiving a clock qualifier signal synchronized with a preselected one of the external clock signals; and (b) an AND gate having inputs coupled to the first recited and the second additional input means and having an output coupled to the second and the additional sampler means and the second memory means.
Claim 10
Dependent Claim
114 words
The composite logic analyzer as recited in claim 3, wherein the first display signal generator circuit comprises: (a) a vertical axis signal generator circuit coupled to the first memory means for generating a vertical axis signal in response to the output data therefrom; (b) a horizontal axis signal generator circuit for generating a horizontal axis signal in the form of a sawtooth voltage synchronized with the vertical axis signal; and (c) a luminance signal generator circuit for generating an unblanking signal during the horizontal scanning periods of the horizontal axis signal, the luminance signal generator circuit being further coupled to the additional memory means for effecting luminance modulation in response to the output therefrom.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-12-13 | 1986-06-14 | 1986-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-12-13 | 1990-06-14 | 1990-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-12-13 | 1994-06-14 | 1994-12-14 | $7700.00 | Window Closed / Lapsed |