Patent US4753208A successfully refreshed from Google Patents.
US4451918A
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US
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Test signal reloader
Assignee: Teradyne Inc
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Filing: 1981-10-09
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Granted: 1984-05-29
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Expires: 2001-10-09
Abstract
Abstract A continuous sequence of test data for testing LSI devices is provided selectably from one of a number of memory elements, each of which is reloaded, when not busy providing test data, from a higher capacity, lower speed storage element.
Inventors
- 👤 Garry C. Gillette
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 23:47
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31919; G01R31/31903; G01R31/31908
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
122 words
Apparatus for providing a continuous sequence of test data for testing LSI devices, each of said devices having a multiplicity of pins, comprising a plurality of memory elements associated with each of said pins, for storing said test data, a random access storage element having higher capacity and lower speed than each of said memory elements, for storing said test data, test sequence control circuitry for routing said test data selectably from any one of said memory elements to its associated said pin, and reloading circuitry for causing a portion of said test data stored in said storage element to be selectably addressed and loaded into any one of said memory elements which is not providing said test data to said pins.
Claim 2
Dependent Claim
122 words
Apparatus for providing a continuous sequence of test data for testing LSI devices, each of said devices having a multiplicity of pins, comprising a plurality of memory elements associated with each of said pins, for storing said test data, a random access storage element having higher capacity and lower speed than each of said memory elements, for storing said test data, test sequence control circuitry for routing said test data selectably from any one of said memory elements to its associated said pin, and reloading circuitry for causing a portion of said test data stored in said storage element to be selectably addressed and loaded into any one of said memory elements which is not providing said test data to said pins.
Claim 3
Dependent Claim
20 words
The apparatus of claim 1 wherein said memory elements comprise static RAMs and said storage element comprises a dynamic RAM.
Claim 4
Dependent Claim
80 words
The apparatus of claim 1 wherein said storage element comprises a plurality of storage sub-elements, and said apparatus further comprises switching circuitry for repeatedly in cycles connecting said storage sub-elements to the memory element being reloaded, and for providing in each of said cycles address information to said storage sub-elements, whereby said test data stored in said storage sub-elements are interleaved and loaded into said memory elements at a rate higher than the effective transfer rate of any individual sub-element.
Claim 5
Dependent Claim
19 words
The apparatus of claim 3 wherein said memory elements comprise static RAMs and said storage sub-elements comprise dynamic RAMs.
Claim 6
Dependent Claim
64 words
The apparatus of claim 3 or 4 wherein said sub-elements are associated in groups and said apparatus further comprises a mass storage memory, for storing said test data, and mass storage switching circuitry for causing said mass storage memory to load a portion of said test data selectably into any one of said groups which is not providing test data to said memory elements.
Claim 7
Dependent Claim
41 words
The apparatus of claim 3 or 4 wherein said test data are loaded from said storage sub-elements into said memory element being reloaded at a rate higher than the rate at which said test data is being routed to said pins.
Claim 8
Dependent Claim
17 words
The apparatus of claim 1, 2, 3 or 4 wherein there are two of said memory elements.
Claim 9
Dependent Claim
69 words
The apparatus of claim 1, 2, 3 or 4 further comprising control apparatus for causing said test sequence control circuitry and said reloading circuitry to alternately route said test data from a first one of said memory elements while loading said test data into another of said memory elements, and loading said test data into said first one while routing said test data from another of said memory elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-29 | 1987-11-28 | 1988-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-29 | 1991-11-28 | 1992-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-29 | 1995-11-28 | 1996-05-29 | $7700.00 | Window Closed / Lapsed |