Magnetic tape data handling system employing dual data block buffers

Claim 3

A system as defined in claim 1 wherein said input/output means includes multiple bit storage means, means responsive to the bits of an externally generated character code word from said external source to generate an additional bit, the value of which is a function of the parity of the incoming code word, and means for entering said incoming code word together with said additional bit in said storage means.

Claim 4

A system as defined in claim 1 wherein said error correction means includes means for generating an error correction command signal and means responsive to the absence of data stored in the input/output means coupled memory unit due to the readout thereof into said principal memory and to the generation of said error correction command signal to switch the state of said selection means, and then to delete a predetermined end portion of the data block in the input/output means coupled memory unit by reversing the recording operation; and further means responsive to said switch-over means to prepare said principal memory to re-store at least a new predetermined end portion in said input/output means coupled memory unit after the data block therein is again completed by additional incoming data.

Claim 5

A system as defined in claim 1 wherein said sensing means comprises means responsive to accumulation in the input/output means coupled memory unit of a predetermined number of data bits to generate a control signal, said second control means being responsive to said control signal to actuate said second transfer means, and said selection means being responsive to said control signal to change from one state to the other.

Claim 6

A system as defined in claim 1 further comprising means for storing a reference code word representing a message termination character, means connected to said reference storage means and said input/output means to compare an incoming character code word with said reference code word, means for generating a coincidence signal when said incoming character code word matches said reference code word, and logic means responsive to said coincidence signal for actuating said second control means and said selection means.

Claim 7

A system as defined in claim 5 wherein said logic means includes means responsive to said coincidence signal for assuring storage in the input/output means coupled memory unit of said message termination character, means responsive to completion of storage of said message termination character to load a succession of format bits of a particular value into said last mentioned memory unit until a complete data block has been accumulated, and means responsive to operation of said sensing means for preventing the loading of format bits.

Claim 8

A system as defined in claim 1 wherein said input/output means includes means for temporarily storing incoming data from said external source; and means responsive to an incoming character code word to transfer a previously received character code word from said input/output storage means one of said said input/output associated memory unit.

Claim 9

A system as defined in claim 1 wherein each of said memory units includes a plurality of separate memory sites for storing the individual bits comprising a data block; and wherein said second transfer means comprises means to actuate each of said memory sites in sequence to provide the contents thereof to said principal memory, means for generating a timing pulse concurrently with the actuation of each memory site, and means for storing said timing pulse in said principal memory together with thE associated data bit.

Claim 12

A system as defined in claim 9 wherein said second transfer means includes first means for providing data to said external utilization device in parallel form with all of the bits defining a character code word appearing simultaneously; second means for providing data to said utilization device in serial form with each of the bits defining a character code word appearing in sequence; wherein said first transfer means is operative to provide data to said input/output means one bit at a time.

Claim 13

A system as defined in claim 9 further including means responsive to detection of an erroneous code word to suppress said erroneous code word, and to substitute another code word therefor.

Claim 14

A system as defined in claim 9 wherein said third control means comprises means responsive to accumulation in said principal memory coupled memory unit of a predetermined number of data bits for temporarily halting data storage therein, means responsive to transfer from said input/output means coupled memory unit to said input/output means of said predetermined number of bits for generating a control signal; said selection means being responsive to said control signal to switch states, and said third transfer means being operative in response to said control signal.

Claim 15

A system as defined in claim 9 wherein the end of a message is identified by a particular terminal character, wherein said third control means includes means for providing a Second control signal in response to transfer of said particular character to said input/output means; and logic means responsive to said second control signal for terminating said playback sequence.

Claim 16

A system as defined in claim 13 wherein said logic means includes means operative to assure switching of said selection means and actuation of said third transfer means to enter a block of data into the principal memory coupled memory unit before said playback sequence is terminated.

Claim 17

A system as defined in claim 13 wherein said input/output means includes means for temporarily storing character code words provided by said input/output means coupled memory unit, means to initiate transfer of a previously stored character code word to said external utilization device, and means responsive to transfer of a character code word from said temporary storage means to transfer another code word to said input/output means from the input/output means coupled memory unit; and wherein said logic means is responsive to said second control signal to assure transfer out of any data stored in said temporary storage means before said playback sequence is terminated.

Claim 18

A system as defined in claim 9 wherein the end of a message is identified by a particular terminal character, wherein said third control means includes means for providing a second control signal in response to transfer of said particular character to said input/output means; and logic means including first and second cycle means, said first cycle means being responsive to said second control signal to prevent utilization by said input/output means of further data transferred from said input/output means coupled memory unit, and said second cycle means being responsive to operation of said first cycle means and to occurrence of the next of said first control signals to prevent transfer of data from the input/output coupled memory unit to the input/output means.

Claim 19

A system as defined in claim 9 wherein said principal memory contains a plurality of control pulses, each data bit being associated with one of said control pulses; wherein each of said intermediate memory units includes a plurality of separate memory sites for storing the bits comprising a data block, wherein said control logic means includes means to operate said principal memory to generate data pulses and the associated control pulses; and means responsive to said control pulses to actuate said memory sites in sequence to transfer the data pulses associated with said control pulses to said sequence of memory sites of said principal memory coupled memory unit.

Claim 20

A system as defined in claim 9 wherein said control logic means includes search operation means for establishing a search operation sequence to locate a particular combination of characters stored in said principal memory, said search operation means comprising means for storing a reference representing said particular combination of characters, means for generating an external search command, means responsive to said search command to initiate the playback operation sequence, further means responsive to said search command to inhibit operation of said second transfer means, means for comparing said stored reference with data provided to said input/output means and for providing a coincidence signal when said particular combination of characters is located, and means responsive to said coincidence signal for terminating said search operation sequence.

Claim 21

A system as defined in claim 18 further including timing means for controlling the rate of data transfer from the input/output means coupled memory unit for the playback operation sequence, said timing means being responsive to said search command to establish a data transfer rate for the search operation equal to the fastest rate available for playback operation.

Claim 22

A system as defined in claim 18 including means responsive to transfer of all available data from said principal memory to terminate said search operation, eveN if said search is not successfully completed.

Claim 23

A memory system for storage and retrieval of information in the form of multibit character code words, comprising input/output means, first coupling means connected to said input/output means and adapted to be connected to an external data source for connecting said data source to said input/output means and second coupling means connected to said input/output means and adapted to be connected to an external data utilization device for connecting said input/output means to said device; intermediate memory means comprising first and second memory units, each having capacity for storing a block of data comprising a number of character code words; data storage means adapted to receive a memory medium as a principal memory for the system; selection means having a first state in which the first memory unit is coupled to the input/output means and the second memory unit is coupled to said data storage means, and a second state in which the second memory unit is coupled to the input/output means and the first memory unit is coupled to said data storage means; first means for transferring data one bit at a time between said input/output means and said first memory unit when said selection means is in said first state, and between said input/output means and said second memory unit when said selection means in in said second state; second means for transferring information one bit at a time between said second memory unit and said data storage means when said selection means is in said first state and between said first memory unit and said data storage means when said selection means is in said second state, and logic means for controlling the information transfer operations for said system.

Claim 24

A memory system for storage and retrieval of information in the form of multibit character code words, comprising input/output means, first coupling means connected to said input/output means and adapted to be connected to an external data source for connecting said data source to said input/output means and second coupling means connected to said input/output means and adapted to be connected to an external data utilization device for connecting said input/output means to said device; intermediate memory means comprising first and second memory units, each having capacity for storing a block of data comprising a number of character code words; data storage means adapted to receive a memory medium as a principal memory for the system; selection means having a first state in which the first memory unit is coupled to the input/output means and the second memory unit is coupled to said data storage means, and a second state in which the second memory unit is coupled to the input/output means and the first memory unit is coupled to said data storage means; first means for transferring data one bit at a time between said input/output means and said first memory unit when said selection means is in said first state, and between said input/output means and said second memory unit when said selection means in in said second state; second means for transferring information one bit at a time between said second memory unit and said data storage means when said selection means is in said first state and between said first memory unit and said data storage means when said selection means is in said second state, and logic means for controlling the information transfer operations for said system.

Claim 25

A system as defined in claim 21 further including clock means for generating primary timing signals, means for selecting a data transfer bit rate for the system, means responsive to said selecting means and to said clock means for generating a first pulse train at a frequency less than the clock frequency corresponding to said selected bit rate; wherein said first coupling means includes means for receiving data one bit at a time at a bit rate which is a sub-multiple of the frequency of said first pulse train; and wherein said logic means includes counter means responsive to said first pulse train and to an actuating signal to generate a series of timing pulses at said sub-multiple frequency with the first pulse in predetermined time relation to said activating signal, sensing means responsive to incoming data to generate said activating signal, and means responsive to said timing pulses for operating said input/output means to accept said incoming data, and to transfer said data to the input/output means coupled intermediate memory unit at a rate determined by said submultiple bit rate.

Claim 26

A system as defined in claim 22 wherein said input/output means includes means for temporarily storing incoming data in response to said timing pulses, and means responsive to said timing pulses for operating said first transfer means to transfer previously stored data bits from said input/output storage means to the input/output coupled intermediate memory unit.

Claim 27

A system as defined in claim 22 including means responsive to said clock means for generating a second pulse train at a frequency substantially exceeding the frequency of said first pulse train, sensing means responsive to accumulation in the input/output means coupled intermediate memory unit of an entire block of data for generating a first control signal, means in said logic means responsive to said first control signal to switch the states of said selection means and further means responsive to said control signal for operating the data storage means coupled intermediate memory unit to transfer data one bit at a time to said data storage means at a bit rate equal to the frequency of said second pulse train.

Claim 28

A system as defined in claim 24 further including means reSponsive to said second pulse train for storing a timing bit in said principal memory means concurrently with each data bit stored therein.

Claim 29

A system as defined in claim 22 wherein each character code word commences with a predetermined non-information bearing bit; wherein said sensing means is responsive to said non-information bearing bit to activate said counter to advance in response to the pulses of said first pulse train, said counter including means to provide a first timing pulse at a predetermined count corresponding to the nominal center of the bit period of the first information bearing bit of the incoming character code word, and means for providing further timing pulses at a succession of counts corresponding to the nominal centers of the bit periods for the other information bearing bits of said incoming character code word, means for collecting said timing pulses to form a train of pulses, and means for deactivating and resetting said counter when a predetermined maximum count is reached.

Claim 30

A system as defined in claim 26 wherein the frequency of said first pulse train is eight times the nominal bit rate.

Claim 31

A system as defined in claim 22 wherein said second coupling means includes means for transmitting data one bit at a time at a bit rate which is a sub-multiple of the frequency of said first pulse train; means in said logic means actuating said counter means to generate said timing pulses at said sub-multiple frequency, means for actuating the input/output means coupled intermediate memory unit, said input/output means and said second coupling means in response to said timing pulses to transfer data from said last mentioned input/output means coupled intermediate memory unit through said input/output means to said utilization device at said sub-multiple frequency.

Claim 32

A system as defined in claim 28 wherein said counter includes means for generating an additional pulse preceding said timing pulses by an interval equal to the interval between data bits at said selected data bit rate, and means responsive to said additional pulse for generating an initial bit for transmission as part of each character code word.

Claim 33

A system as defined in claim 23 further including means responsive to said clock means to generate a second pulse train at a frequency substantially higher than the frequency of said first pulse train, means responsive to said second pulse train for generating a second series of timing pulses; wherein said second transfer means includes means for storing one of said second timing pulses concurrently with a data bit in said principal memory, means for retrieving said second timing pulses, means responsive to said retrieved second timing pulses for activating said second transfer means to enter data from the principal memory into the data storage means coupled intermediate memory unit; and further including means responsive to accumulation in said last mentioned intermediate memory unit of an amount of data equal to the storage capacity thereof generating a control signal, means responsive to said control signal for switching the state of said selection means, and thereafter for actuating said first transfer means to transfer data from the input/output means coupled intermediate memory unit one bit at a time to said input/output means, further means responsive to said control signal for reactuating said second transfer means to enter further data from said principal memory to said data storage means coupled intermediate memory unit while data from said input/output means coupled intermediate memory is being transferred to said input/output means.

Claim 34

A system as defined in claim 30 wherein the end of a complete message is identified by a particular terminal character, wherein said logic means includes means responsive to the presence of a terminal character in said input/output means to generate a second control signal, means responsive to said second control signal to actuate said second coupling means to transfeR said terminal character to said external utilization device, means for thereafter preventing operation of said second coupling means, means responsive to transfer of said terminal character to said external utilization device for operating the input/output means coupled intermediate memory unit to transfer the data therein to said input/output unit means.

Claim 35

A system, as defined in claim 31 further including means responsive to the completion of the transfer of the contents of said input/output means coupled memory unit to said input/output means for switching the state of said selection means, and for thereafter actuating said second transfer means to enter additional data from said principal memory to the data storage means coupled intermediate memory unit.

Claim 36

A system as defined in claim 31 wherein the transfer of data from said last mentioned input/output means coupled memory unit after detection of said terminal character in said input/output means is at a rate substantially exceeding the frequency of said first pulse train.

Claim 37

A system as defined in claim 21 wherein the end of a complete message is identified by a particular terminal character, wherein said sensing means includes means responsive to the presence of said terminal character in said input/output means to generate a second control signal, means responsive to said second control signal to actuate said first transfer means to enter said terminal character in the input/output means coupled intermediate memory unit, means responsive to entry of said terminal character and to the total number of characters in said last mentioned input/output mean coupled memory unit to enter additional characters into said memory unit, and means responsive to entry of a complete data block in said last mentioned input/output means coupled memory unit to prevent entry of additional characters, to switch the state of said selection means, and thereafter to operate said second transfer means to transfer the contents of the data storage means coupled intermediate memory unit to said data storage means.

Claim 38

A system as defined in claim 21 wherein said memory medium comprises a magnetic recording tape: wherein said data storage means includes tape transport means and drive means for said transport means; wherein said second transfer means includes first and second recording circuits for recording first and second information tracks; and wherein said logic means includes means for generating a data transfer pulse train, means to initiate a data record operation sequence comprising means for activating said transport drive means for continuous operation, means for operating the data storage means coupled intermediate memory unit in response to said data transfer pulse train to transfer data to said first recording circuit in bit-by-bit synchronism with said data transfer pulses, and means for coupling said data transfer pulse train to said second recording circuit to store a track of timing pulses on said tape with the timing pulses in synchronism with the bits of said data track.

Claim 39

A system as defined in claim 35 wherein said logic means further includes means responsive to transfer of the entire contents of the data storage means coupled intermediate memory unit to the tape for deactivating said transport drive means.

Claim 40

A system as defined in claim 35 including means responsive to activation of said transport drive means to delay the actuation of the data storage means coupled intermediate memory unit and said recording circuits for a predetermined interval to allow said transport to reach its normal operating speed.

Claim 41

A system as defined in claim 35 wherein said first and second recording circuits include means for converting the binary code input to a non-return-to-zero code for recording.

Claim 42

A system as defined in claim 35 wherein said second transfer means includes first and second playback circuits associated with the first and second information tracks of a tape serving as the principal meMory medium, and wherein said logic means includes means to initiate a data playback sequence comprising means for actuating said transport drive means for continuous operation, means for connecting said first playback circuit to the data storage means coupled intermediate memory unit, means connected to said second playback circuit and responsive to timing pulses in said second tape information track for activating said data storage means coupled intermediate memory unit to store the data bit associated with each timing pulse, and means responsive to playback of a block of data equal to the capacity of the data storage means coupled intermediate memory unit for deactivating said transport drive means.

Claim 43

A system as defined in claim 39 wherein said deactivating means comprises means for stopping said transport drive means after a predetermined interval if timing pulses are not detected by said second playback circuit.

Claim 44

A system as defined in claim 39 wherein said deactivating means comprises means for counting the number of data bits entered in the data storage means coupled memory unit and means for stopping said transport drive when a predetermined bit count has been reached.

Claim 45

A system as defined in claim 39 including means responsive to actuation of said transport drive means to delay activation of the data storage means coupled intermediate memory unit for a predetermined tape start-up interval to allow said transport to reach its normal operating speed, and means for inhibiting operation of said deactivating means during said start-up delay interval.

Claim 46

A system as defined in claim 42 wherein said logic means includes means connected to said second playback circuit and responsive to an externally generated command to override said deactivation means until a timing pulse has been played back from said timing track through said second playback circuit.

Claim 47

A memory system as defined in claim 21 wherein said second transfer means is adapted to retrieve data from a magnetic tape serving as said principal memory medium, said tape having recorded thereon a first track of data pulses and a second track of timing pulses synchronized with said data pulses, groups of said pulses being separated by blank portions of said tape to define individual blocks of data having a number of bits equal to the capacity of said intermediate memory units, wherein said second transfer means includes separate playback circuits for said data and timing tracks; wherein said data storage means comprises magnetic tape transport means and transport drive means; and wherein said logic means includes means for establishing a playback operating sequence comprising means for activating said transport drive means, control means responsive to timing pulses played back by said timing track playback circuit to activate the data storage coupled intermediate memory unit to store a data pulse associated with each timing pulse, and cycle termination means responsive to playback of an entire data block for deactivating said transport drive means and for preventing further storage of data in said data storage means coupled intermediate memory unit.

Claim 48

A system as defined in claim 44 including means responsive to actuation of said transport drive means to prevent storage of data in said data storage means coupled; memory unit and to inhibit said cycle termination means for a predetermined start-up delay period to allow said transport to reach its normal operating speed.

Claim 49

A system as defined in claim 45 wherein said logic means includes means for establishing a load operation sequence comprising means responsive to an external load command to activate said transport drive means and to deactivate said cycle termination means, and means responsive to the start of playback of information by said second transfer means to reactivate said cycle termination means.

Claim 50

A system as defined in claim 46 wherein said means for reactivating said cycle termination means is responsive to the fIrst timing track pulse of a data block.

Claim 51

A system as defined in claim 21 wherein said input/output means includes storage means for at least one multibit character code word, wherein said first coupling means comprises means for receiving incoming character code words in serial form at several different nominal bit rates, wherein said logic means includes means for generating a first pulse train at a frequency which is a high multiple of the highest of said nominal bit rates, dividing means responsive to said first pulse train to generate a second pulse train at a frequency equal to a selected nominal bit rate, means responsive to the first bit of an incoming character code word to generate an activating signal for said dividing means, said dividing means being operative to generate the first pulse of said second pulse train after a predetermined number of pulses of said first pulse train following said activating signal, and for generating succeeding pulses of said second pulse train at a frequency equal to said nominal bit rate, means for activating said input/output storage means in response to said second pulse train to store incoming data bits in synchronism with the pulses of said second pulse train, and means for deactivating said dividing means after a predetermined number of pulses of said second pulse train have been generated.

Claim 52

A system as defined in claim 48 wherein said first coupling means includes means for receiving incoming code words in parallel form, wherein said logic means includes means responsive to appearance of a code word in parallel form in said first coupling means to generate said activating signal for said dividing means and also to generate a parallel data entry control signal, means responsive to said parallel data entry control signal to enter the bits of said incoming code word simultaneously into said input/output storage means, said input/output storage means thereafter being responsive to said second pulse train to transfer data stored therein into the intermediate memory unit coupled to said input/output means on a bit-by-bit basis.

Claim 53

A system as defined in claim 21 wherein said data storage means includes transport means for receiving a magnetic tape as said memory medium, and drive means for said tape transport, said drive means including means for operating said transport in a forward direction, means for operating said transport in a reverse direction, means cooperating with said transport for sensing the beginning of a tape, and means cooperating with said transport for sensing the end of a tape; and werein said logic means includes means for actuating said forward drive means during data transfer between said data means and the data storage means coupled memory unit and means responsive to the sensing of the end of a tape for deactivating said forward drive means.

Claim 54

A system as defined in claim 50 including means for generating an external rewind command signal and wherein said logic means includes means responsive to said external rewind command signal to operate said reverse drive means, and means responsive to the sensing of the beginning of the tape for deactivating said reverse drive means.

Claim 55

A system as defined in claim 51 further including means for generating an external tape erase command signal and wherein said logic means includes means for establishing a tape erase operation sequence comprising means responsive to said external tape erase command signal to operate said forward drive means, means responsive to sensing of the end of the tape and to said tape erase command signal to deactivate said forward drive means and to activate said reverse drive means, means in said second data transfer means responsive to said tape erase command signal to erase the tape, and means responsive to the sensing of the beginning of the tape and said tape erase command signal to terminate said erase operation sequence.

Claim 56

A system as defined in claim 50 further including means for generating an eXternal tape erase command signal and means responsive to said external tape erase command signal for operating said data storage means to erase all information stored on a tape adapted to be carried by said transport.

Claim 57

A system as defined in claim 21 including means for generating an external error command signal and wherein said logic means includes means responsive to said external error correction command signal to delete a character code word from the input/output means coupled intermediate memory unit.

Claim 58

A system as defined in claim 21 wherein said data storage means is adapted to receive a magnetic tape cassette as said principal memory medium.

Claim 59

A system as defined in claim 21 wherein said input/output means further includes means coupled thereto to detect the existence of an error in a character to be transferred to said utilization device, and means responsive to detection of an error for preventing transfer of the erroneous code word.

Claim 60

A system as defined in claim 21 wherein said input/output means includes a shift register having a number of stages sufficient to store an entire character code word; means responsive to said incoming character code word from an external serial data source for operating said shift register and the input/output means coupled intermediate memory units to enter said incoming code word bit by bit into said shift register and to transfer a code word previously entered in said shaft register one bit at a time to said intermediate memory unit.

Claim 61

A system as defined in claim 57 wherein said input/output means includes means for connecting the bits of an incoming character code word from a parallel data source simultaneously to respective stages of said shift register and wherein said logic means includes means for entering said code word into said shift register stages and for thereafter advancing said shift register a sufficient number of times to transfer said code word one bit at a time to said input/output means coupled intermediate memory unit.

Claim 62

A system as defined in claim 57 wherein said input/output means includes means responsive to the bits of an incoming code word to generate an additional bit, the value of which is a function of the parity of the incoming code word, and means for entering said additional bit in one of the bit positions of said shift register, together with the associated code word.

Claim 63

A system as defined in claim 21 wherein each of said intermediate memory units comprises a random access memory having a plurality of individually accessible memory sites, said random access memory being operable in storage and retrieval operating modes, and means for selectively activating said individual memory sites for storage or retrieval operation.

Claim 64

A system as defined in claim 21 wherein each of said intermediate memory units includes a plurality of individually accessible memory sites, said memory units being selectively operable to store a data bit in an addressed memory site or to read out a data bit from an addressed memory site, means coupled to each of said memory units to address the individual memory sites thereof and further means coupled to each of said memory units to select storage or read-out operation for a particular memory site addressed by said addressing means.

Claim 65

A system as defined in claim 21 wherein said logic means includes means for establishing data storage and retrieval modes of operation for the system, means for generating signals indicative of the selected mode, means responsive to said storage mode signal to activate said first coupling means, said input/output means, said first transfer means, and said input/output means coupled intermediate memory unit to store data in said input/output means coupled memory unit, means responsive to storage in said input/output means coupled memory unit of a complete data block from said input/output means for switching the state of said selection means, and for activating said data storage means, said second tRansfer means, and said data storage means coupled intermediate memory unit to transfer the data therein to said data storage means, and means responsive to the transfer of a block of data to said data storage means to deactivate said second transfer means, said data storage means, and the data storage means coupled intermediate memory unit.

Claim 66

A system as defined in claim 62 wherein each of said intermediate memory units includes a plurality of individually accessible memory sites, said memory units being selectively operable to write a data bit in an addressed memory site or to read out a data bit from an addressed memory site, means coupled to each of said memory units to address the individual memory sites thereof in a particular sequence, means responsive to the arrival of data at said input/otput means to advance the addressing means for the input/output means coupled intermediate memory unit through a portion of its sequence, read/write control means coupled to each of said memory units to select read or write operation for a particular memory site addressed by said addressing means, and wherein said logic means includes means cooperating with said read/write control means for the first intermediate memory unit and responsive to said storage mode signal to operate said first memory unit to write data when the selection means is in its first state, and to read out data when the selection means is in the second state, and means cooperating with the read/write control means for said second memory unit and responsive to said storage mode signal to operate said second memory unit to read data when the selection means is in its first state, and to write data when the selection means is in the second state.

Claim 67

A system as defined in claim 63 further including means for generating an error command signal and error correction means comprising countback means responsive to said external error command signal and to said storage mode signal for operating the addressing means for the input/output means coupled memory unit to re-address the memory site corresponding to the first bit of the last character entered in said input/output means coupled memory unit, whereby the portion of the address sequence corresponding to the last entered character is repeated when new data appears at said input/output means.

Claim 68

A system as defined in claim 64 wherein said addressing means is an up-down counter, wherein said advancing means is operative to advance said counter on a step-by-step basis by a number of counts equal to the number of bits to be stored in the associated memory unit, and wherein said countback means comprises means to reduce the count in said counter by a number of counts equal to the number of bits to be corrected.

Claim 69

A system as defined in claim 64 including switch-over means responsive to said error correction command signal, and to a predetermined address state of the input/output means coupled memory unit to switch the state of the selection means whereby the intermediate memory unit previously coupled to said data storage means becomes coupled to the input/output means and further including means responsive to said error correction signal for maintaining the address of the intermediate memory unit now coupled to said input/output means at the address corresponding to the last available memory site until operation of said count-back means commences.

Claim 70

A system as defined in claim 66 further including means responsive to operation of said switch-over means to prepare said principal memory to re-record at least a portion of the last data block transferred thereto.

Claim 71

A system as defined in claim 67 wherein said memory medium is a magnetic tape, wherein said data storage means includes tape transport means operable in a forward direction to receive data transferred from one of said intermediate memory units, and wherein said enabling means comprises means responsive to operation of said switch-over means to operate said tape in a reverse directioN until the entire portion of the tape containing the previously recorded data block has been rewound.

Claim 72

A memory system as defined in claim 63 further comprising means for storing a reference code word representing a message termination character, means connected to said reference storage means and said input/output means to compare an incoming character code word with said reference code word, means for generating a coincidence signal when said incoming character code word matches said reference code word, and logic means responsive to said coincidence signal for actuating the address advancing means for the input/output means coupled memory unit to assure storage therein of said message termination character, means responsive to completion of storage of said message termination character to operate the address advancing means for the input/output means coupled memory unit to load a succession of format bits therein of a particular value, and means responsive to accumulation of a complete data block for preventing the loading of format bits.

Claim 73

A system as defined in claim 69 wherein said means for preventing the loading of formatting bits comprises means responsive to the addressing means for the input/output means coupled memory unit reaching the address corresponding to the last available memory site of the input/output means coupled intermediate memory unit to inhibit the operation of said loading means.

Claim 74

A system as defined in claim 21 wherein said logic means includes means for establishing data storage and retrieval modes of operation for the system, means for generating signals indicative of the selected mode, means responsive to a retrieval mode signal to activate said second coupling means, said input/output means, said first transfer means, and said input/output means coupled intermediate memory unit to transfer data from said input/output means coupled memory unit through said input/output means to an external data utilization device, means responsive to transfer from said input/output means coupled memory unit of a complete data block to said input/output means for switching the state of said selection means, and for activating said principal memory, said second transfer means, and said data storage means coupled intermediate memory unit to transfer another data block from said principal memory to the intermediate memory unit coupled to said data storage means and means responsive to the transfer of said block of data from said principal memory to deactivate said second transfer means, said principal memory, and the intermediate memory unit coupled to said data storage means.

Claim 75

A system as defined in claim 71 wherein each of said intermediate memory units includes a plurality of individually accessible memory sites, said memory units being selectively operable to write a data bit in an addressed memory site or to read out a data bit from an addressed memory site, means coupled to each of said memory units to address the individual memory sites thereof in a particular sequence, read/write control means coupled to each of said memory units to select read or write operation for a particular memory site addressed by said addressing means, and wherein said logic means includes means cooperating with the read/write control means for said first intermediate memory unit and responsive to said retrieval mode signal to operate said first memory unit to read out data when the selection means is in its first state, and to write data when the selection means is in the second state, and means cooperating with the read/write control means for said second memory unit and responsive to said retrieval mode signal to operate said second memory unit to write data when the selection means is in its first state, and to read out data when the selection means is in the second state.

Claim 76

A system as defined in claim 72 wherein the end of a complete message is identified by a particular terminal character, and wherein said logic means includes means foR storing a reference code word corresponding to said message termination character, means connected to said reference storage means and said input/output means to compare an outgong character code word with said reference code word, means for generating a coincidence signal when said outgoing character code word matches said reference code word, and logic means responsive to said coincidence signal for actuating the address advancing means for the input/output means coupled memory unit to continue the same through its operating sequence, means for sensing the end of said operating sequence, and means responsive to the end of said operating sequence for terminating the operation of said address advancing means.

Claim 77

A system as defined in claim 71 wherein the beginning of a message is identified by a multiple character recognition code, and wherein said logic means includes means for establishing a search mode of operation to locate a particular recognition code comprising means for storing reference characters constituting a recognition code, means for generating an external search command signal and means responsive to said external search command signal, and to said retrieval mode signal to enter said storage means, a particular recognition code, means responsive to completion of entry in said storage means of said recognition code for initiating operation of the system in its removal data retrieval mode, means for comparing the contents of the data provided to said input/output means by the intermediate memory unit coupled thereto with said stored recognition code, means responsive to a match between said recognition code, and the data in said input/output means to terminate said search operation.

Claim 78

A memory system for storage and retrieval of information in the form of multibit character code words, comprising input/output means, first coupling means adapted to receive data from an external data source, and adapted to provide data to an external data utilization device; intermediate memory means comprising first and second memory units, each having capacity for storing a block of data comprising a number of character code words, each of said intermediate memory units having a plurality of individually accessible memory sites, said memory units being selectively operable to write a data bit in an addressed memory site or to read out a data bit from an addressed memory site; counter means associated with each of said memory units to address the individual memory sites thereof; read/write control means coupled to each of said memory units to select read or write operation for an addressed memory site; data storage means comprising transport means adapted to handle a magnetic tape as a principal memory for said system, record circuitry for coupling data to said tape, and playback circuitry for receiving data from said tape; selection means having a first state in which the first memory unit is coupled to the input/output means and the second memory unit is coupled to said data storage means, and a second state in which the second memory unit is coupled to the input/ouput means and the first memory unit is coupled to said data storage means; mode selection means for establishing data storage and retrieval modes of system operation, and for providing signals representative of the selected mode; clock means for generating a first pulse train, an actuating signal, counter means responsive to said first pulse train and to said actuating signal to generate a series of timing pulses with the first of said timing pulses in predetermined time relation to said actuating signal; first transfer means for transferring data between said input/output means and the input/output means coupled memory unit; second transfer means including said record and playback circuitry for transferring data between the data storage means coupled memory unit and said data storage means; data transfer control means responsive to said mode selection signals for operating the read/write control meanS, said first and second transfer means, and said intermediate memory units such that, when the respective address counters are operated, the input/output means coupled memory unit is conditioned to write data for the information storage mode of operation, and to read out data for the information retrieval mode of operation, and the data storage means coupled memory unit is conditioned to read out data for the information storage mode of operation, and to write data for the information retrieval mode of operation; means responsive to said data storage mode signal and to incoming data to generate said actuating signal for said timing pulse generating counter; means for generating an external playback initiation signal; means responsive to said retrieval mode signal and to said external playback initiation signal to generate a succession of said actuating signals for said timing pulse generating counter; means responsive to said timing pulses to advance the addressing counter for the input/output means coupled memory unit one count for each timing pulse, means responsive to a predetermined first count in the addressing counter for the input/output means coupled memory unit corresponding to the address of the last memory site to generate a first switching signal; means responsive to said first switching signal to switch the state of said selection means; means responsive to said first switching signal to reset the address counters for said first and second memory units to a predetermined second count corresponding to the address of the first memory site; further means responsive to said first switching signal to start said tape transport; means responsive to operation of said tape transport and said first pulse train to generate a control pulse train; means responsive to said control pulse train and said storage mode signal for advancing the address counter for the data storage means coupled memory unit; means adapted to store on the tape, each control pulse along with the corresponding data pulse for the data storage means coupled memory unit; means responsive to said retrieval mode signal and to control pulses stored on said tape to advance the address counter for the data storage means coupled memory unit; means responsive to said predetermined first count in the address counter for the data storage means coupled memory unit and to said storage mode signal to generate a second switching signal; and means responsive to said second switching signal to stop said tape transport and to terminate said control pulse train.

Claim 79

A memory system for storage and retrieval of information in the form of multibit character code words, comprising input/output means, first coupling means adapted to receive data from an external data source, and adapted to provide data to an external data utilization device; intermediate memory means comprising first and second memory units, each having capacity for storing a block of data comprising a number of character code words, each of said intermediate memory units having a plurality of individually accessible memory sites, said memory units being selectively operable to write a data bit in an addressed memory site or to read out a data bit from an addressed memory site; counter means associated with each of said memory units to address the individual memory sites thereof; read/write control means coupled to each of said memory units to select read or write operation for an addressed memory site; data storage means comprising transport means adapted to handle a magnetic tape as a principal memory for said system, record circuitry for coupling data to said tape, and playback circuitry for receiving data from said tape; selection means having a first state in which the first memory unit is coupled to the input/output means and the second memory unit is coupled to said data storage means, and a second state in which the second memory unit is coupled to the input/ouput means and the first memory unit is coupled to said data storage means; mode selection means for establishing data storage and retrieval modes of system operation, and for providing signals representative of the selected mode; clock means for generating a first pulse train, an actuating signal, counter means responsive to said first pulse train and to said actuating signal to generate a series of timing pulses with the first of said timing pulses in predetermined time relation to said actuating signal; first transfer means for transferring data between said input/output means and the input/output means coupled memory unit; second transfer means including said record and playback circuitry for transferring data between the data storage means coupled memory unit and said data storage means; data transfer control means responsive to said mode selection signals for operating the read/write control meanS, said first and second transfer means, and said intermediate memory units such that, when the respective address counters are operated, the input/output means coupled memory unit is conditioned to write data for the information storage mode of operation, and to read out data for the information retrieval mode of operation, and the data storage means coupled memory unit is conditioned to read out data for the information storage mode of operation, and to write data for the information retrieval mode of operation; means responsive to said data storage mode signal and to incoming data to generate said actuating signal for said timing pulse generating counter; means for generating an external playback initiation signal; means responsive to said retrieval mode signal and to said external playback initiation signal to generate a succession of said actuating signals for said timing pulse generating counter; means responsive to said timing pulses to advance the addressing counter for the input/output means coupled memory unit one count for each timing pulse, means responsive to a predetermined first count in the addressing counter for the input/output means coupled memory unit corresponding to the address of the last memory site to generate a first switching signal; means responsive to said first switching signal to switch the state of said selection means; means responsive to said first switching signal to reset the address counters for said first and second memory units to a predetermined second count corresponding to the address of the first memory site; further means responsive to said first switching signal to start said tape transport; means responsive to operation of said tape transport and said first pulse train to generate a control pulse train; means responsive to said control pulse train and said storage mode signal for advancing the address counter for the data storage means coupled memory unit; means adapted to store on the tape, each control pulse along with the corresponding data pulse for the data storage means coupled memory unit; means responsive to said retrieval mode signal and to control pulses stored on said tape to advance the address counter for the data storage means coupled memory unit; means responsive to said predetermined first count in the address counter for the data storage means coupled memory unit and to said storage mode signal to generate a second switching signal; and means responsive to said second switching signal to stop said tape transport and to terminate said control pulse train.

Claim 80

A system as defined in claim 75 including means responsive to said first switching signal to delay the generation of the control pulse train, and to inhibit operation of said recording circuit for a predetermined interval to allow said tape transport to reach its normal operating speed.

Claim 81

A system as defined in claim 76 including means connected to said playback circuit for sensing control pulses recorded on said tape, means for stopping said tape transport after a predetermined interval if control pulses are not detected by said sensing means; and means for inhibiting operation of said transport stopping means during the predetermined start-up delay interval.

Claim 82

A system as defined in claim 77 further including means for establishing a load operation sequence comprising means responsive to an external load command to place said selection means in its second state and to said retrieval mode signal to activate said transport drive means and to deactivate said transport stopping means; means responsive to the next control pulse detected by said sensing means to reactivate said transport stopping means; and means responsive to said external load command to said first count in the address counter for said first intermediate memory unit to generate said first switching signal.

Claim 83

A memory system as defined in claim 75 wherein said second transfer means includes first and second record and first and second playback circuits, said first reCord circuit and said first playback circuit being associated with a first tape track for data pulses, and a second record circuit and said second playback circuit being associated with a separate tape track for recording said control pulses.

Claim 84

A system as defined in claim 75 wherein said input/output means is adpated to accept incoming character code words serially commencing with a predetermined non-information bearing bit; wherein said means to activate said timing pulse generating counter is responsive to said non-information bearing bit in an incoming character code word; said counter including means to provide a first timing pulse at a predetermined count corresponding to the nominal center of the bit period of the first information bearing bit of the incoming character code word; means for providing further timing pulses at a succession of counts corresponding to the nominal centers of the bit periods for the other information bearing bits of said incoming character code word, means for collecting said timing pulses to form said series of pulses, and means for deactivating and resetting said counter when a predetermined maximum count is reached.

Claim 85

A system as defined in claim 80 wherein said input/output means is adapted to accept incoming code words in parallel form, wherein said means to actuate said timing pulse generating counter is responsive to appearance of a code word in parallel form to generate said actuating signal, and also to generate a parallel data entry control signal, means responsive to said parallel data entry control signal to enter the bits of said incoming code word simultaneously into said input/output means, and means responsive to said series of timing pulses to transfer data from said input/output means into the input/output means coupled intermediate memory unit on a bit-by-bit basis.

Claim 86

A system as defined in claim 81 wherein said input/output means comprises a shift register having a number of stages sufficient to store an entire character code word, and wherein said first coupling means includes means adapted to couple data serially between said shift register and serial external equipment and in parallel between said shift register and parallel external equipment; and wherein said first transfer means comprises means for coupling data serially between said shift register and the input/output means coupled memory unit.

Claim 87

A system as defined in claim 81 wherein said first coupling means includes means for transmitting data one bit at a time at a bit rate which is equal to the repetition rate of said timing pulses; and wherein said timing pulse generating counter includes means for generating an additional pulse preceding said timing pulses by an interval equal to the interval between data bits at said data bit rate, and means responsive to said additional pulse for generating an initial bit for transmission as part of each character code word.

Claim 88

A system as defined in claim 75 including error correction control logic comprising means for generating an error correction signal, means responsive to said error correction signal and to said storage mode signal to generate said actuating signal for said timing pulse generating counter; and means responsive to said error correction signal to operate the address counter for the input/output means coupled memory unit in a reverse direction in response to each of said timing pulses.

Claim 89

A memory system as defined in claim 84 wherein said error correction control means includes means responsive to said predetermined second count in the address counter for the input/output means coupled memory unit to generate said first switching signal; means responsive to said error correction signal to inhibit reset of said intermediate memory address counters in response to said first switching signal; means responsive to said first switching signal and said error correction signal to operate said tape transport unit in a reverse direction; means for actuating said playback circuit dUring said reverse operation; means connected to said playback circuit for sensing recorded control pulses; and means for stopping said tape transport after a predetermined interval if control pulses are not detected by said sensing means.

Claim 90

A system as defined in claim 75 including means for establishing a search mode of operation for locating a recognition code comprising a combination of characters stored in said tape comprising reference character storage means; means for generating a reference storage signal; means responsive to said reference storage signal, to said retrieval mode signal, and to incoming data to store said data in said character storage means; means responsive to storage of said recognition code in said character storage means for generating a search operation signal and said playback initiation signal; means responsive to said search operation signal to inhibit operation of said first coupling means; means for comparing data provided to said input/output means from said input/output means coupled memory unit with the data contained in said character storage means and for generating a coincidence signal when said data match; and means responsive to said coincidence signal for terminating said search operation.

Claim 91

A system as defined in claim 86 wherein said system is capable of handling data at a variety of data rates; and wherein said clock means is operative to provide said first pulse train during a search operation at a frequency such that the repetition rate of said timing pulses is equal to or greater than the maximum data bit rate at which the system can operate.

Claim 92

A system as defined in claim 86 wherein said character storage means comprises a plurality of latch circuits, one of said latch circuit being provided for each bit of said recognition code; means for coupling said latch circuits to said input/output means; and means for actuating said latch circuits to receive data from said input/output means when an incoming character is present.

Claim 93

A system as defined in claim 88 wherein said input/output means includes a shift register having a sufficient number of bit positions to store the complete recognition code; wherein each of said latch circuits is connected to one of the shift register bit positions; and wherein said comparing means comprises a plurality of individual comparator circuits connected to one of said latch circuits and to the corresponding bit position of the shift register.

Claim 94

A system as defined in claim 75 wherein the end of a complete message is identified by a particular terminal character; and further including means connected to said input/output means for sensing said terminal character and for generating a coincidence signal when said character is detected, means responsive to said coincidence signal for generating an actuating signal for said timing pulse generating counter; means responsive to said storage mode signal and the last one of a series of timing pulses following said coincidence signal to generate a series of control pulses; means for operating the address counter for the input/output associated memory unit in response to said second control pulse train; and means responsive to said first switching signal for preventing generation of said series of control pulses.

Claim 95

A system as defined in claim 90 further including means responsive to said coincidence signal and said retrieval mode signal for generating said actuating signal for said timing pulse generating counter; and means responsive to the last one of a series of timing pulses following said coincidence signal for preventing further operation of timing pulse generating counter.

Claim 96

A system as defined in claim 75 wherein the frequency of said control pulse train substantially exceeds the repetition rate for said series of timing pulses.