US3781829A
Expired / Lapsed
US
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Test pattern generator
Assignee: International Business Machines Corp
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Filing: 1972-06-16
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Granted: 1973-12-25
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Expires: 1992-06-16
Abstract
Abstract A test pattern generator comprising a memory means for storing n test pattern numbers. The memory means is responsive to a selectively alterable address means for generating a plurality of distinct test pattern sequence of numbers from the n stored test pattern numbers.
Inventors
- 👤 S Singh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:23
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/31813; G06; G06F; G06F1/00; G06F1/02; G06F1/03
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
184 words
A test pattern generator comprising: a. memory means having a plurality of fixed storage locations for storing a plurality of n test pattern numbers, b. address storage means connected to said memory means and having input terminals for receiving an original fixed address signal, and being responsive to said original fixed address signal for generating a first test pattern sequence of numbers from said plurality of n test pattern numbers stored in said plurality of fixed storage locations, c. said address storage means further including control means for firstly altering the state of said original fixed address signal for generating a first unique address signal, and sequentially thereafter being sequentially responsive to said control means for generating a successive sequence of m unique addresS signals by successively altering a preceding unique address signal, and d. said memory means being responsive to said first unique address signal and to each of said m successive sequence of new address signals for generating m+1 mutually distinct test patterns sequence of numbers from said plurality of n test pattern numbers stored in said plurality of fixed storage locations.
Claim 2
Dependent Claim
184 words
A test pattern generator comprising: a. memory means having a plurality of fixed storage locations for storing a plurality of n test pattern numbers, b. address storage means connected to said memory means and having input terminals for receiving an original fixed address signal, and being responsive to said original fixed address signal for generating a first test pattern sequence of numbers from said plurality of n test pattern numbers stored in said plurality of fixed storage locations, c. said address storage means further including control means for firstly altering the state of said original fixed address signal for generating a first unique address signal, and sequentially thereafter being sequentially responsive to said control means for generating a successive sequence of m unique addresS signals by successively altering a preceding unique address signal, and d. said memory means being responsive to said first unique address signal and to each of said m successive sequence of new address signals for generating m+1 mutually distinct test patterns sequence of numbers from said plurality of n test pattern numbers stored in said plurality of fixed storage locations.
Claim 3
Dependent Claim
36 words
A test pattern generator as in claim 1 wherein said address storage means comprises: a. an X writable decode circuit connected to said memory means and a Y writable decode circuit connected to said memory means.
Claim 4
Dependent Claim
27 words
A test pattern generator as in claim 2 further including: a. means for writing said original fixed address signal into said X and Y writable decode circuits.
Claim 5
Dependent Claim
82 words
A test pattern generator as in claim 3 wherein: a. said control means further includes counter means connected to said X and Y writable decode circuits and being adapted to receive a series of basic clock pulses, said counter means and said X and Y writable decode circuits being responsible to a basic series of clock pulses for selectively reading said first test pattern sequence of numbers from said plurality of n test pattern numbers stored in said plurality of fixed locations.
Claim 6
Dependent Claim
70 words
A test pattern generator as in claim 4 wherein: a. said counter means further includes circuit means responsive to another clock rate lower than the basic clock rate for selectively altering the states of said X and Y writable decode circuits for generating said first unique address signal and said successive sequence of m unique address signals for reading said m+1 test pattern sequence of numbers from said memory means.
Claim 7
Dependent Claim
35 words
A test pattern generator as in claim 5 wherein: a. said counter means comprises an X counter connected to said X writable decode circuit, and a Y counter connected to said Y writable decode circuit.
Claim 8
Dependent Claim
86 words
A test pattern generator as in claim 6 wherein: a. said X and Y counters each include circuit means for generating respective clock rates lower than the basic clock rate, and interconnection means between said X counter, said X writable decode circuit, said Y counter, and said Y writable decode circuit for applying the reduced clock rates to said X and Y writable decode circuits for selectively generating variable addresses therein comprising said first unique address signal and said successive sequence of m unique address signals.
Claim 9
Dependent Claim
18 words
A test pattern generator as in claim 7 wherein: a. said memory means comprises a read-only memory means.
Claim 10
Dependent Claim
18 words
A test pattern generator as in claim 7 wherein: a. said memory means comprises a read-write memory means.
References Cited (Backward Citations)
US3444526A
Cited
US3588830A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-12-24 | 1977-06-25 | 1977-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-12-24 | 1981-06-25 | 1981-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-12-24 | 1985-06-25 | 1985-12-25 | $7700.00 | Window Closed / Lapsed |