US3715573A
Expired / Lapsed
US
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Failure activity determination technique in fault simulation
Assignee: International Business Machines Corp
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Filing: 1971-04-14
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Granted: 1973-02-06
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Expires: 1991-04-14
Abstract
Abstract The failure activity determination technique of the present application represents a new approach to fault simulation designed to significantly reduce the time required to perform such simulations. This new technique may be used in conjunction with any interpretive fault simulation program (i.e., any program using list structures to trace and calculate circuit activity in a logic design). The improved technique consists essentially of using previously calculated good machine values during the fault simulation for any logic blocks that are not effected by the failure(s) being simulated. Thus, new values must be calculated for only a subset of the total logic circuitry. This subset, or failure partition, of the logic is determined dynamically during the fault simulation through the use of a series of flags within the circuit list structure.
Inventors
- 👤 R Vogelsberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:03
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
604 words
A method for determining detectable failure data concerning an electronic logic circuit having a plurality of interconnected logic blocks from which data, maintenance procedures may be established, comprising the steps of preparing a sequence of test patterns on an input-output storage device, executing in a general purpose data processing system a three-valued, unit-delay, interpretive good machine simulation under control of said sequence of test patterns, preparing, on an input-output device, an all events trace which includes an ordered listing of all test patterns and all logical values changes in the logic blocks in the sequence in which they occurred during the good machine simulation, of the time periods at which they occurred and of entries directing comparison of good vs. failure machine values at specified outputs of the circuit being simulated; preparing a list of failures on an input-output device, storing in the system a circuit description of the circuit inputs, selected outputs, and logic blocks in the system, executing in the system a three-valued, unit-delay, interpretive good and failure machine simulation under control of said all events trace for each failure in the list, the latter simulation including the steps of dynamically determining the failure partition, i.e. those logic blocks affected by the failure at any moment during simulation, dynamically assigning different flags to logic blocks within and outside of the failure partition, dynamically updating, under control of the flags, the values of inputs and logic blocks not in the failure partition incident to all events trace entries, and dynamically calculating, under control of the flags, the values of only those logic blocks in the failure partition incident to all events trace entries and circuit value propagation, periodically comparing good and failure machine values at selected circuit outputs for detection of simulated failures, and storing detected failure data in an input-output device. 2. A method for determining detectable failure data concerning an electronic logic circuit having a plurality of interconnected logic blocks from which data, maintenance procedures may be established, comprising the steps of preparing a sequence of test patterns on an input-oUtput storage device, executing in a general purpose data processing system good machine simulation under control of said sequence of test patterns, preparing, on an input-output device, an all events trace which includes an ordered listing of all test patterns and all logical values changes in the logic blocks in the sequence in which they occurred during the good machine simulation, of the time periods at which they occurred and of entries directing comparison of good vs. failure machine values at specified outputs of the circuit being simulated; preparing a list of failures on an input-output device, storing in the system a circuit description of the circuit inputs, selected outputs, and logic blocks in the system, executing in the system an at least partially, interpretive good and failure machine simulation under control of said all events trace for each failure in the list, the latter simulation including the steps of dynamically determining the failure partition, i.e. those logic blocks affected by the failure at any moment during simulation, dynamically assigning different flags to logic blocks within and outside of the failure partition, dynamically updating, under control of the flags, the values of inputs and logic blocks not in the failure partition incident to all events trace entries, and dynamically calculating, under control of the flags, the values of only those logic blocks in the failure partition incident to all events trace entries and circuit value propagation, periodically comparing good and failure machine values at selected circuit outputs for detection of simulated failures, and storing detected failure data in an input-output device.
Claim 2
Independent Claim
604 words
A method for determining detectable failure data concerning an electronic logic circuit having a plurality of interconnected logic blocks from which data, maintenance procedures may be established, comprising the steps of preparing a sequence of test patterns on an input-output storage device, executing in a general purpose data processing system a three-valued, unit-delay, interpretive good machine simulation under control of said sequence of test patterns, preparing, on an input-output device, an all events trace which includes an ordered listing of all test patterns and all logical values changes in the logic blocks in the sequence in which they occurred during the good machine simulation, of the time periods at which they occurred and of entries directing comparison of good vs. failure machine values at specified outputs of the circuit being simulated; preparing a list of failures on an input-output device, storing in the system a circuit description of the circuit inputs, selected outputs, and logic blocks in the system, executing in the system a three-valued, unit-delay, interpretive good and failure machine simulation under control of said all events trace for each failure in the list, the latter simulation including the steps of dynamically determining the failure partition, i.e. those logic blocks affected by the failure at any moment during simulation, dynamically assigning different flags to logic blocks within and outside of the failure partition, dynamically updating, under control of the flags, the values of inputs and logic blocks not in the failure partition incident to all events trace entries, and dynamically calculating, under control of the flags, the values of only those logic blocks in the failure partition incident to all events trace entries and circuit value propagation, periodically comparing good and failure machine values at selected circuit outputs for detection of simulated failures, and storing detected failure data in an input-output device. 2. A method for determining detectable failure data concerning an electronic logic circuit having a plurality of interconnected logic blocks from which data, maintenance procedures may be established, comprising the steps of preparing a sequence of test patterns on an input-oUtput storage device, executing in a general purpose data processing system good machine simulation under control of said sequence of test patterns, preparing, on an input-output device, an all events trace which includes an ordered listing of all test patterns and all logical values changes in the logic blocks in the sequence in which they occurred during the good machine simulation, of the time periods at which they occurred and of entries directing comparison of good vs. failure machine values at specified outputs of the circuit being simulated; preparing a list of failures on an input-output device, storing in the system a circuit description of the circuit inputs, selected outputs, and logic blocks in the system, executing in the system an at least partially, interpretive good and failure machine simulation under control of said all events trace for each failure in the list, the latter simulation including the steps of dynamically determining the failure partition, i.e. those logic blocks affected by the failure at any moment during simulation, dynamically assigning different flags to logic blocks within and outside of the failure partition, dynamically updating, under control of the flags, the values of inputs and logic blocks not in the failure partition incident to all events trace entries, and dynamically calculating, under control of the flags, the values of only those logic blocks in the failure partition incident to all events trace entries and circuit value propagation, periodically comparing good and failure machine values at selected circuit outputs for detection of simulated failures, and storing detected failure data in an input-output device.
Claim 3
Independent Claim
604 words
A method for determining detectable failure data concerning an electronic logic circuit having a plurality of interconnected logic blocks from which data, maintenance procedures may be established, comprising the steps of preparing a sequence of test patterns on an input-output storage device, executing in a general purpose data processing system a threevalued, unit-delay, interpretive good machine simulation under control of said sequence of test patterns, preparing, on an input-output device, an all events trace which includes an ordered listing of all test patterns and all logical values changes in the logic blocks in the sequence in which they occurred during the good machine simulation, of the time periods at which they occurred and of entries directing comparison of good vs. failure machine values at specified outputs of the circuit being simulated; preparing a list of failures on an input-output device, storing in the system a circuit description of the circuit inputs, selected outputs, and logic blocks in the system, executing in the system a three-valued, unit-delay, interpretive good and failure machine simulation under control of said all events trace for each failure in the list, the latter simulation including the steps of dynamically determining the failure partition, i.e. those logic blocks affected by the failure at any moment during simulation, dynamically assigning different flags to logic blocks within and outside of the failure partition, dynamically updating, under control of the flags, the values of inputs and logic blocks not in the failure partition incident to all events trace entries, and dynamically calculating, under control of the flags, the values of only those logic blocks in the failure partition incident to all events trace entries and circuit value propagation, periodically comparing good and failure machine values at selected circuit outputs for detection of simulated failures, and storing detected failure data in an input-output device. 2. A method for determining detectable failure data concerning an electronic logic circuit having a plurality of interconnected logic blocks from which data, maintenance procedures may be established, comprising the steps of preparing a sequence of test patterns on an input-oUtput storage device, executing in a general purpose data processing system good machine simulation under control of said sequence of test patterns, preparing, on an input-output device, an all events trace which includes an ordered listing of all test patterns and all logical values changes in the logic blocks in the sequence in which they occurred during the good machine simulation, of the time periods at which they occurred and of entries directing comparison of good vs. failure machine values at specified outputs of the circuit being simulated; preparing a list of failures on an input-output device, storing in the system a circuit description of the circuit inputs, selected outputs, and logic blocks in the system, executing in the system an at least partially, interpretive good and failure machine simulation under control of said all events trace for each failure in the list, the latter simulation including the steps of dynamically determining the failure partition, i.e. those logic blocks affected by the failure at any moment during simulation, dynamically assigning different flags to logic blocks within and outside of the failure partition, dynamically updating, under control of the flags, the values of inputs and logic blocks not in the failure partition incident to all events trace entries, and dynamically calculating, under control of the flags, the values of only those logic blocks in the failure partition incident to all events trace entries and circuit value propagation, periodically comparing good and failure machine values at selected circuit outputs for detection of simulated failures, and storing detected failure data in an input-output device.
Claim 4
Independent Claim
604 words
A method for determining detectable failure data concerning an electronic logic circuit having a plurality of interconnected logic blocks from which data, maintenance procedures may be established, comprising the steps of preparing a sequence of test patterns on an input-output storage device, executing in a general purpose data processing system a threevalued, unit-delay, interpretive good machine simulation under control of said sequence of test patterns, preparing, on an input-output device, an all events trace which includes an ordered listing of all test patterns and all logical values changes in the logic blocks in the sequence in which they occurred during the good machine simulation, of the time periods at which they occurred and of entries directing comparison of good vs. failure machine values at specified outputs of the circuit being simulated; preparing a list of failures on an input-output device, storing in the system a circuit description of the circuit inputs, selected outputs, and logic blocks in the system, executing in the system a three-valued, unit-delay, interpretive good and failure machine simulation under control of said all events trace for each failure in the list, the latter simulation including the steps of dynamically determining the failure partition, i.e. those logic blocks affected by the failure at any moment during simulation, dynamically assigning different flags to logic blocks within and outside of the failure partition, dynamically updating, under control of the flags, the values of inputs and logic blocks not in the failure partition incident to all events trace entries, and dynamically calculating, under control of the flags, the values of only those logic blocks in the failure partition incident to all events trace entries and circuit value propagation, periodically comparing good and failure machine values at selected circuit outputs for detection of simulated failures, and storing detected failure data in an input-output device. 2. A method for determining detectable failure data concerning an electronic logic circuit having a plurality of interconnected logic blocks from which data, maintenance procedures may be established, comprising the steps of preparing a sequence of test patterns on an input-oUtput storage device, executing in a general purpose data processing system good machine simulation under control of said sequence of test patterns, preparing, on an input-output device, an all events trace which includes an ordered listing of all test patterns and all logical values changes in the logic blocks in the sequence in which they occurred during the good machine simulation, of the time periods at which they occurred and of entries directing comparison of good vs. failure machine values at specified outputs of the circuit being simulated; preparing a list of failures on an input-output device, storing in the system a circuit description of the circuit inputs, selected outputs, and logic blocks in the system, executing in the system an at least partially, interpretive good and failure machine simulation under control of said all events trace for each failure in the list, the latter simulation including the steps of dynamically determining the failure partition, i.e. those logic blocks affected by the failure at any moment during simulation, dynamically assigning different flags to logic blocks within and outside of the failure partition, dynamically updating, under control of the flags, the values of inputs and logic blocks not in the failure partition incident to all events trace entries, and dynamically calculating, under control of the flags, the values of only those logic blocks in the failure partition incident to all events trace entries and circuit value propagation, periodically comparing good and failure machine values at selected circuit outputs for detection of simulated failures, and storing detected failure data in an input-output device.
Claim 5
Independent Claim
273 words
A method for determining detectable failure data concerning an electronic logic circuit having a plurality of interconnected logic blocks from which data, maintenance procedures may be established, comprising the steps of preparing a sequence of test patterns, executing a three-valued, unit-delay, interpretive good machine simulation under control of said sequence of test patterns, preparing an all events trace which includes an ordered listing of all test patterns and all logical values changes in the logic blocks in the sequence in which they occurred during the good machine simulation, of the time periods at which they occurred and of entries directing comparison of good vs. failure machine values at specified outputs of the circuit being simulated; preparing a list of failures, storing a circuit description of the circuit inputs, selected outputs, and logic blocks in the system, executing a three-valued, unit-delay, interpretive good and failure machine simulation under control of said all events trace for each failure in the list, the latter simulation including the steps of dynamically determining the failure partition, i.e. those logic blocks affected by the failure at any moment during simulation, dynamically assigning different flags to logic blocks within and outside of the failure partition, dynamically updating, under control of the flags, the values of inputs and logic blocks not in the failure partition incident to all events trace entries, and dynamically calculating, under control of the flags, the values of only those logic blocks in the failure partition incident to all events trace entries and circuit value propagation, periodically comparing good and failure machine values at selected circuit outputs for detection of simulated failures, and storing detected failure data.
Claim 6
Independent Claim
273 words
A method for determining detectable failure data concerning an electronic logic circuit having a plurality of interconnected logic blocks from which data, maintenance procedures may be established, comprising the steps of preparing a sequence of test patterns, executing a three-valued, unit-delay, interpretive good machine simulation under control of said sequence of test patterns, preparing an all events trace which includes an ordered listing of all test patterns and all logical values changes in the logic blocks in the sequence in which they occurred during the good machine simulation, of the time periods at which they occurred and of entries directing comparison of good vs. failure machine values at specified outputs of the circuit being simulated; preparing a list of failures, storing a circuit description of the circuit inputs, selected outputs, and logic blocks in the system, executing a three-valued, unit-delay, interpretive good and failure machine simulation under control of said all events trace for each failure in the list, the latter simulation including the steps of dynamically determining the failure partition, i.e. those logic blocks affected by the failure at any moment during simulation, dynamically assigning different flags to logic blocks within and outside of the failure partition, dynamically updating, under control of the flags, the values of inputs and logic blocks not in the failure partition incident to all events trace entries, and dynamically calculating, under control of the flags, the values of only those logic blocks in the failure partition incident to all events trace entries and circuit value propagation, periodically comparing good and failure machine values at selected circuit outputs for detection of simulated failures, and storing detected failure data.
Claim 7
Dependent Claim
189 words
In a fault simulation program for simulating digital systems within a processor to predict and document the behavior of the system in the presence of predetermined logic failures for given input test patterns of the type in which a record is made of every input and logic block value change occurring during a simulated non-failing behavior of the system under control of a sequence of test patterns applied tHereto, in which input, output and logic block value changes occurring during a simulated good and failing behavior of the system under control of said record and a selected failure are determined, and in which selected outputs are periodically checked for differences between good and failing machine values to detect the selected failures, wherein the determination of the value changes for said simulated good and failing behavior comprises the steps of dynamically determining those logic blocks affected by the selected failure as simulation proceeds, dynamically updating the values of the inputs and logic blocks not affected by the selected failure as simulation proceeds, and dynamically calculating the values of only those logic blocks affected by the selected failure as simulation proceeds.
Claim 8
Dependent Claim
189 words
In a fault simulation program for simulating digital systems within a processor to predict and document the behavior of the system in the presence of predetermined logic failures for given input test patterns of the type in which a record is made of every input and logic block value change occurring during a simulated non-failing behavior of the system under control of a sequence of test patterns applied tHereto, in which input, output and logic block value changes occurring during a simulated good and failing behavior of the system under control of said record and a selected failure are determined, and in which selected outputs are periodically checked for differences between good and failing machine values to detect the selected failures, wherein the determination of the value changes for said simulated good and failing behavior comprises the steps of dynamically determining those logic blocks affected by the selected failure as simulation proceeds, dynamically updating the values of the inputs and logic blocks not affected by the selected failure as simulation proceeds, and dynamically calculating the values of only those logic blocks affected by the selected failure as simulation proceeds.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-06 | 1976-08-07 | 1977-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-06 | 1980-08-07 | 1981-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-06 | 1984-08-07 | 1985-02-06 | $7700.00 | Window Closed / Lapsed |