Method and apparatus for modeling systems of complex circuits

Claim 2

In an apparatus for modeling operation of a digital system as a simulation model responsive to a sequence of clock cycles, a method for modeling operation of a complex digital device within said simulation model, said method comprising: presenting input signals as a sequence of digital patterns in synchronization with clock signals to a reference element, said reference element being a physical sample of said digital device; stopping the presentation of said sequence of patterns at a preselected clock cycle unrelated to states of said reference element; sampling output signals of said reference element at a defined clock edge after a last one of said input patterns in a sequence in order to allow said simulation system to respond to final values of said output signals; storing a next input pattern in said sequence of patterns in a memory, said next pattern being a response to said simulation system response; resetting said reference element; and repeating the presentation of said input signals beginning with patterns following an initial resetting and incrementing the number of clock cycles of said sequence until an entire sequence of patterns has been presented to the reference element within time constraints for operating the reference element.

Claim 3

The method according to claim 1 wherein said resetting step comprises activating a reset signal line of said reference element.

Claim 4

The method according to claim 1 wherein said resetting step comprised as presenting a preselected pattern or sequence of patterns of signals to said reference element.

Claim 5

The method according to claim 1 wherein said presenting step occurs at a clock rate which differs from a clock rate associated with operating said simulation system.

Claim 6

The method according to claim 1 wherein said sampling step includes sampling said output signals after a delay greater than a specified maximum delay for change in any output signal.

Claim 7

The method according to claim 1, further including the step of dumping internal states of said reference element and said resetting step comprises restoring internal states of said reference element in response to predefined input sequence signals in order to generate output signals corresponding to known patterns at known cycles of said reference element without response to all input sequence patterns following said resetting step.

Claim 8

The method according to claim 1, further including the step of providing high-impedance terminations of input terminals and output terminals of said reference element.

Claim 9

The method according to claim 1 wherein said reference element includes time-shared input/output terminals and wherein said method further includes the step of sensing fully states of said input/output terminals.

Claim 10

The method according to claim 1, further including the step of prestoring said sequence of input signals prior to said presenting step in a memory means.

Claim 11

The method according to claim 9, further including the step of prestoring repetitive segments of said sequence of input signals as a single segment.

Claim 12

For use in an apparatus for modeling operation of a digital system as a simulation model responsive to a sequence of clock cycles, an apparatus for modeling operation of at least one complex digital device, including a dynamic device, within said simulation model, said apparatus comprising input register means for temporarily storing at least a single parallel pattern of input signals; means for coupling a sample of said device to be modeled as a reference element to receive said input signals representative of a predetermined sequence of input patterns from said input register means; means coupled to said reference element coupling means for controlling clocking of said reference element independent of said simulation model, said clock controlling means being operative to start, cycle and stop operation of said reference element at preselectable clock cycles unrelated to states of said reference element; means coupled to said reference element coupling means for presenting said sequence of input patterns; said presenting means being operative to reset said devices to repeatedly present said sequence of input patterns to said device and to increment the number of clock cycles of said sequence with each new input pattern prior to repeating prior segments of said sequence until an entire sequence of input patterns has been presented to said reference element; means coupled to said reference element coupling means for sampling output signals of said reference element at a defined time after a last one of said input patterns in a sequence; and means coupled to said presenting means and responsive to said simulation model for receiving and storing a next input pattern in said sequence.

Claim 13

For use in an apparatus for modeling operation of a digital system as a simulation model responsive to a sequence of clock cycles, an apparatus for modeling operation of at least one complex digital device, including a dynamic device, within said simulation model, said apparatus comprising input register means for temporarily storing at least a single parallel pattern of input signals; means for coupling a sample of said device to be modeled as a reference element to receive said input signals representative of a predetermined sequence of input patterns from said input register means; means coupled to said reference element coupling means for controlling clocking of said reference element independent of said simulation model, said clock controlling means being operative to start, cycle and stop operation of said reference element at preselectable clock cycles unrelated to states of said reference element; means coupled to said reference element coupling means for presenting said sequence of input patterns; said presenting means being operative to reset said devices to repeatedly present said sequence of input patterns to said device and to increment the number of clock cycles of said sequence with each new input pattern prior to repeating prior segments of said sequence until an entire sequence of input patterns has been presented to said reference element; means coupled to said reference element coupling means for sampling output signals of said reference element at a defined time after a last one of said input patterns in a sequence; and means coupled to said presenting means and responsive to said simulation model for receiving and storing a next input pattern in said sequence.

Claim 14

The apparatus according to claim 11 wherein said presenting means is operative for activating a reset means of said device prior to repeating prior segments of said sequence.

Claim 15

The apparatus according to claim 11 wherein said presenting means is operative for activating a predefined resetting pattern or sequence of patterns coupled to a reset means of said device prior to repeating prior segments of said sequence.

Claim 16

The apparatus according to claim 11 wherein said sampling means includes means for providing high-impedance terminations of input terminals and output terminals of said reference element.

Claim 17

The apparatus according to claim 11 wherein said presenting means includes means for storing at least a segment of said input pattern sequence for presenting said input pattern sequence at a controlled rate to said reference element, said controlled rate being greater than a rate of receipt of input pattern signals by said storing means.