Method for fabricating buried channel field-effect transistor for microwave and millimeter frequencies

Claim 1

A process for fabricating a field effect transistor, comprising the steps of: (a) supplying a semi-insulating semiconductor wafer having an upper and lower surface, and a right-hand, central and left-hand region, (b) growing an epitaxial N+ layer on the upper surface of the semi-insulating wafer, (c) providing a proton bombardment mask, said mask being positioned over the upper surface of the device and said mask having a first, second, and third opening, the first opening being positioned over the area immediately surrounding the right-hand, left-hand and central regions, the second opening being positioned over the boundary between the right-hand and central regions, the third being positioned over the boundary between the left-hand and central regions, (d) providing a source of proton bombardment directed at the N+ layer exposed by the openings in the proton bombardment mask to convert the exposed N+ areas to semi-insulating areas, which divide the N+ layer into corresponding right-hand, central and left-hand N+ regions, (e) growing an N layer over the upper surface of the device, (f) growing a semi-insulating layer over the N layer, (g) removing the semi-insulating layer over the central region to expose the N layer, which forms the gate of the field effect transistor, (h) removing a portion of the semi-insulating and N layers over the left and right-hand N+ regions to expose a portion of the N+ regions, the right and left-hand N+ regions forming the drains of the field effect transistor, and (i) making contact with the N+ layer in the central region which forms the source of the field effect transistor.