US4244097A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Schottky-gate field-effect transistor and fabrication process therefor
Assignee: The AT&T MVPD Group LLC
•
Filing: 1979-03-15
•
Granted: 1981-01-13
•
Expires: 1999-03-15
Abstract
Abstract The specification describes a Schottky-gate field-effect transistor and related fabrication process wherein thin ion implanted surface stabilization regions are formed between source and gate electrodes and gate and drain electrodes of the device and to a thickness of between 100 and 1,000 angstroms. This is accomplished utilizing the source, gate and drain electrodes as an ion implantation mask against impinging inert ions which render the implanted regions semi-insulating, and this process requires no postimplantation annealing.
Inventors
- 👤 Frederick W. Cleary
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:47
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/206; H10D; H10D30/00; H10D30/80; H10D30/87; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/161; H10P30/208; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/918
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
93 words
A process for fabricating a surface stabilized Schottky-gate field-effect transistor which comprises depositing source, gate and drain electrodes on the surface of a III-V compound semiconductor crystal to expose certain surface areas thereof, and then implanting chosen inert ions into said exposed surface areas using each of the electrodes as a mask to form lattice damaged and electrically compensated thin regions of controlled depth beneath the surface of said crystal, whereby the effects of carrier traps and defects in the semiconductor crystal surface are minimized, thereby reducing device drift, time constants and noise.
Claim 2
Dependent Claim
93 words
A process for fabricating a surface stabilized Schottky-gate field-effect transistor which comprises depositing source, gate and drain electrodes on the surface of a III-V compound semiconductor crystal to expose certain surface areas thereof, and then implanting chosen inert ions into said exposed surface areas using each of the electrodes as a mask to form lattice damaged and electrically compensated thin regions of controlled depth beneath the surface of said crystal, whereby the effects of carrier traps and defects in the semiconductor crystal surface are minimized, thereby reducing device drift, time constants and noise.
Claim 3
Dependent Claim
25 words
The process defined in claim 1 wherein xenon is implanted into a gallium arsenide crystal to a depth of between a 100 and 1,000 angstroms.
Claim 4
Dependent Claim
100 words
A process for reducing the magnitude of temporal drift in the parameters of drain current, noise figure, gain, and also reducing the total time required for temporal drift to cease in a metal-III-IV compound semiconductor field effect transistor having spaced apart source, gate and drain electrodes on the surface of a semiconductor crystal, comprising implanting selected inert ions into areas of said semiconductor crystal only between said source-and-gate and gate-and-drain electrodes to a predetermined controlled depth less than 1000 angstroms, thereby creating very thin semi-insulating regions in said crystal of between 10 4 -10 8 ohm. centimeters in bulk resistivity.
Claim 5
Dependent Claim
100 words
A process for reducing the magnitude of temporal drift in the parameters of drain current, noise figure, gain, and also reducing the total time required for temporal drift to cease in a metal-III-IV compound semiconductor field effect transistor having spaced apart source, gate and drain electrodes on the surface of a semiconductor crystal, comprising implanting selected inert ions into areas of said semiconductor crystal only between said source-and-gate and gate-and-drain electrodes to a predetermined controlled depth less than 1000 angstroms, thereby creating very thin semi-insulating regions in said crystal of between 10 4 -10 8 ohm. centimeters in bulk resistivity.
Claim 6
Dependent Claim
24 words
The process defined in claim 3 wherein xenon is implanted into a gallium arsenide crystal to a depth of between 100 and 1000 angstroms.
References Cited (Backward Citations)
US3700978A
Cited
US3912546A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-13 | 1984-07-14 | 1985-01-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-13 | 1988-07-14 | 1989-01-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-13 | 1992-07-14 | 1993-01-13 | $7700.00 | Window Closed / Lapsed |