US3700978A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Field effect transistors and methods for making field effect transistors
Assignee: AT&T Inc
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Filing: 1971-03-18
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Granted: 1972-10-24
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Expires: 1991-03-18
Abstract
Abstract The insulative gate layer of an insulated gate field effect transistor (IGFET) is made by exposing a channel region of a semiconductor wafer to high energy proton bombardment. The bombardment damages the crystal structure of the semiconductor to a predetermined depth to make that part of the semiconductor nonconductive.
Inventors
- 👤 James Clayton North
- 👤 Bernard Roger Pruniaux
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:12
CPC Classifications
H; H10; H10P; H10P34/00; H10P34/40; H10D; H10D30/00; H10D30/60; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10P30/00; H10P30/20; H10P30/202; H10P30/206; H10P30/208; Y; Y10; Y10S; Y10S148/00; Y10S148/126
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
133 words
The method for making an insulated gate field effect transistor comprising the steps of growing an epitaxial layer of less than 1.3 microns thickness on a semi-insulative substrate of gallium-arsenide; forming source and drain contacts on the epitaxial layer; forming an insulative gate layer comprising the step of irradiating the epitaxial layer surface between the source and drain contacts with protons having sufficient energy to penetrate the epitaxial layer and convert it to insulating material, but having insufficient energy to penetrate through the metal source and drain contacts, whereby the contacts act as a mask to said radiation; the radiation penetration defining a transistor channel between the insulative gate layer and the semi-insulative substrate having a thickness of less than one micron; and forming a metal gate contact on the insulative gate layer.
Claim 2
Independent Claim
133 words
The method for making an insulated gate field effect transistor comprising the steps of growing an epitaxial layer of less than 1.3 microns thickness on a semi-insulative substrate of gallium-arsenide; forming source and drain contacts on the epitaxial layer; forming an insulative gate layer comprising the step of irradiating the epitaxial layer surface between the source and drain contacts with protons having sufficient energy to penetrate the epitaxial layer and convert it to insulating material, but having insufficient energy to penetrate through the metal source and drain contacts, whereby the contacts act as a mask to said radiation; the radiation penetration defining a transistor channel between the insulative gate layer and the semi-insulative substrate having a thickness of less than one micron; and forming a metal gate contact on the insulative gate layer.
Claim 3
Dependent Claim
126 words
An insulated gate field effect transistor comprising: a gallium-arsenide wafer comprising a semi-insulative substrate and an epitaxial upper layer; dispLaced source and drain electrodes on the surface of the epitaxial upper layer; a gate electrode between the source and drain electrodes; the gate electrode being substantially electrically insulated from the wafer by an insulative gate layer comprising a region of the epitaxial upper layer which has been irradiated with protons of sufficient energy to substantially disrupt and damage the crystal lattice structure of the layer to a predetermined depth; the epitaxial upper layer having a thickness of less than 1.3 microns; and the semiconductor region between the semi-insulative substrate and the insulative gate layer constituting a transistor channel having a thickness of less than one micron.
Claim 4
Dependent Claim
126 words
An insulated gate field effect transistor comprising: a gallium-arsenide wafer comprising a semi-insulative substrate and an epitaxial upper layer; dispLaced source and drain electrodes on the surface of the epitaxial upper layer; a gate electrode between the source and drain electrodes; the gate electrode being substantially electrically insulated from the wafer by an insulative gate layer comprising a region of the epitaxial upper layer which has been irradiated with protons of sufficient energy to substantially disrupt and damage the crystal lattice structure of the layer to a predetermined depth; the epitaxial upper layer having a thickness of less than 1.3 microns; and the semiconductor region between the semi-insulative substrate and the insulative gate layer constituting a transistor channel having a thickness of less than one micron.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-24 | 1976-04-24 | 1976-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-24 | 1980-04-24 | 1980-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-24 | 1984-04-24 | 1984-10-24 | $7700.00 | Window Closed / Lapsed |