US4156879A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Passivated V-gate GaAs field-effect transistor
Assignee: Raytheon Co
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Filing: 1977-02-07
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Granted: 1979-05-29
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Expires: 1997-02-07
Abstract
Abstract The specification describes a new and improved Schottky-gate field-effect transistor (FET) and process for fabricating same wherein selective and multiple ion implantation doping steps are used to form source, drain and channel regions in a semiconductor body. The semiconductor body is then selectively etched to expose the source and drain regions previously formed, while leaving intact a mesa-shaped, high resistivity stabilizing region of the semiconductor body overlying and electrically stabilizing the ion-implanted channel region. The semiconductor body is then partially passivated with a chosen dielectric layer having two openings therein for exposing source and drain regions, respectively, and a third opening which is aligned with the channel region. Ohmic contacts are deposited in the source and drain openings, and thereafter a V-shaped groove is etched in the mesa-shaped region overlying the channel region to expose a very small area of the channel region. Schottky-gate metallization is then deposited in this V-shaped groove to form the Schottky-gate electrode of the device, and the fully passivated device thus formed exhibits excellent source and drain contact resistance and a minimum of drain-to-gate capacitance.
Inventors
- 👤 Don H. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 21:10
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/87; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; Y; Y10; Y10S; Y10S148/00; Y10S148/049; Y10S148/051; Y10S148/088; Y10S148/139; Y10S148/15
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
170 words
A field-effect transistor including in combination: (a) a semiconductor body having heavily doped ion implanted and buried source and drain regions separated by and joined at opposite ends of a lightly doped ion implanted and buried channel region, (b) a high resistivity semiconductor region within said semiconductor body and located atop said channel region and having an opening therein exposing a desired contact area of said channel region, (c) a dielectric passivation layer extending over portions of said source and drain regions and said high resitivity semiconductor region for electrically stabilizing said field-effect transistor, said passivation layer having openings therein exposing portions of said source, drain and channel regions, and (d) source and drain ohmic contact metallization disposed respectively in openings of said passivating layer exposing said source and drain regions and Schottky-gate metallization disposed in direct contact with said channel region, whereby current flow in said channel region is within the interior of said semiconductor body and beneath said high resistivity semiconductor region and away from the surface thereof.
Claim 2
Dependent Claim
170 words
A field-effect transistor including in combination: (a) a semiconductor body having heavily doped ion implanted and buried source and drain regions separated by and joined at opposite ends of a lightly doped ion implanted and buried channel region, (b) a high resistivity semiconductor region within said semiconductor body and located atop said channel region and having an opening therein exposing a desired contact area of said channel region, (c) a dielectric passivation layer extending over portions of said source and drain regions and said high resitivity semiconductor region for electrically stabilizing said field-effect transistor, said passivation layer having openings therein exposing portions of said source, drain and channel regions, and (d) source and drain ohmic contact metallization disposed respectively in openings of said passivating layer exposing said source and drain regions and Schottky-gate metallization disposed in direct contact with said channel region, whereby current flow in said channel region is within the interior of said semiconductor body and beneath said high resistivity semiconductor region and away from the surface thereof.
Claim 3
Dependent Claim
29 words
The device defined in claim 1 wherein said opening in said high resistivity semiconductor region is in the form of a V-shaped groove whose apex receives said Schottky-gate metallization.
Claim 4
Dependent Claim
21 words
The device defined in claim 1 wherein said high resistivity semiconductor region is a mesa region bounded by said passivation layer.
Claim 5
Dependent Claim
29 words
The device defined in claim 3 wherein said opening in said high resistivity semiconductor region is in the form of a V-shaped groove whose apex receives said Schottky-gate metallization.
Claim 6
Dependent Claim
146 words
A field-effect transistor including a semiconductor body having doped ion implanted and buried source and drain regions therein separated by and joined at opposite ends of a more lightly doped ion implanted buried channel region which extends between said source and drain regions, a high resistivity semiconductor region within said semiconductor body and located atop said channel region and having an opening therein exposing a desired contact area of said channel region, insulating means disposed atop selected portions of said source, drain and high resistivity semiconductor regions for providing surface passivation for said transistor, said insulating means including openings therein exposing selected areas of said source and drain regions, and source, drain and gate electrodes disposed respectfully in said openings in said insulating means and in said opening in said high resistivity semiconductor region for receiving bias or modulating potentials necessary for operating said field-effect transistor.
Claim 7
Dependent Claim
146 words
A field-effect transistor including a semiconductor body having doped ion implanted and buried source and drain regions therein separated by and joined at opposite ends of a more lightly doped ion implanted buried channel region which extends between said source and drain regions, a high resistivity semiconductor region within said semiconductor body and located atop said channel region and having an opening therein exposing a desired contact area of said channel region, insulating means disposed atop selected portions of said source, drain and high resistivity semiconductor regions for providing surface passivation for said transistor, said insulating means including openings therein exposing selected areas of said source and drain regions, and source, drain and gate electrodes disposed respectfully in said openings in said insulating means and in said opening in said high resistivity semiconductor region for receiving bias or modulating potentials necessary for operating said field-effect transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-05-28 | 1982-11-27 | 1983-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-05-28 | 1986-11-27 | 1987-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-05-28 | 1990-11-27 | 1991-05-29 | $7700.00 | Window Closed / Lapsed |