Method of manufacturing a semiconductor integrated circuit device which includes at least one V-groove jfet and one bipolar transistor

Claim 3

The method of manufacturing a semiconductor integrated circuit device as defined in claim 1, wherein said one principal surface of said semiconductor substrate has a crystal orientation of silicon in the {100} face, and said groove portion is V-shaped in cross-section.

Claim 4

In a method of manufacturing a semiconductor integrated circuit device which includes at least one junction field-effect transistor and at least one bipolar transistor, and includes the steps of: a. providing a semiconductor substrate having first and second isolated regions of a first conductivity type which extend to a first principal surface of said substrate; b. simultaneously diffusing an impurity of a second conductivity type, opposite said first conductivity type, into selected surface portions of said first and second isolated regions, respectively, so as to form third and fourth semiconductor regions of said second conductivity type; and c. simultaneously diffusing an impurity of said first conductivity type into selected surface portions of said third and fourth semiconductor regions, respectively, to form fifth and sixth semiconductor regions of said first conductivity type; said first, third and fifth semiconductor regions being the collector, base, and emitter regions of a bipolar transistor, and the distance between said first and fifth regions defining the base width and the current gain h FE of said bipolar transistor; said fourth and sixth semiconductor regions being the respective gate and channel regions of a junction type field-effect transistor, and the distance between said sixth region and said second region controlling the pinch-off voltage V p of said junction field-effect transistor, the improvement comprising a method for reducing the pinch-off voltage V p to a value smaller than the base-emitter reverse breakdown voltage V BE of said bipolar transistor without reducing the base width and increasing the current gain h FE of said bipolar transistor comprising the step of i. forming a groove in a selected surface portion of said fourth semiconductor region; and ii. forming said sixth region in step (c) by diffusing an impurity of said first conductivity type in the surface portion of said fourth region at the bottom of said groove therein, so that said sixth region extends deeper into said fourth region from said first principal surface than said fifth region extends into said third region.

Claim 5

In a method of manufacturing a semiconductor integrated circuit device which includes at least one junction field-effect transistor and at least one bipolar transistor, and includes the steps of: a. providing a semiconductor substrate having first and second isolated regions of a first conductivity type which extend to a first principal surface of said substrate; b. simultaneously diffusing an impurity of a second conductivity type, opposite said first conductivity type, into selected surface portions of said first and second isolated regions, respectively, so as to form third and fourth semiconductor regions of said second conductivity type; and c. simultaneously diffusing an impurity of said first conductivity type into selected surface portions of said third and fourth semiconductor regions, respectively, to form fifth and sixth semiconductor regions of said first conductivity type; said first, third and fifth semiconductor regions being the collector, base, and emitter regions of a bipolar transistor, and the distance between said first and fifth regions defining the base width and the current gain h FE of said bipolar transistor; said fourth and sixth semiconductor regions being the respective gate and channel regions of a junction type field-effect transistor, and the distance between said sixth region and said second region controlling the pinch-off voltage V p of said junction field-effect transistor, the improvement comprising a method for reducing the pinch-off voltage V p to a value smaller than the base-emitter reverse breakdown voltage V BE of said bipolar transistor without reducing the base width and increasing the current gain h FE of said bipolar transistor comprising the step of i. forming a groove in a selected surface portion of said fourth semiconductor region; and ii. forming said sixth region in step (c) by diffusing an impurity of said first conductivity type in the surface portion of said fourth region at the bottom of said groove therein, so that said sixth region extends deeper into said fourth region from said first principal surface than said fifth region extends into said third region.

Claim 6

The improvement according to claim 3, wherein said first principal surface of said substrate has the crystal orientation of the {100} face of silicon, and said groove is V-shaped in cross-section.