US4266233A
Expired / Lapsed
US
⏱️ 0.0 years remaining
I-C Wafer incorporating junction-type field-effect transistor
Assignee: STMicroelectronics SRL
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Filing: 1979-12-14
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Granted: 1981-05-05
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Expires: 1999-12-14
Abstract
Abstract A silicon wafer incorporating several semiconductor components, among them a junction-type field-effect transistor (J-FET) of low pinch-off voltage connectable as a resistor, comprises a substrate of P-type conductivity with an insular layer of N + conductivity penetrated by one or more enclaves of substrate material. Thereafter, a stratum of N-doped silicon is epitaxially grown on the substrate, with formation of rising zones above each enclave and around the buried N + layer which are heavily doped with P-type impurities to act as source connections or sinkers for an FET channel formed by the enclave or enclaves and as a barrier junction surrounding a section of the N-doped stratum which becomes the gate of the FET while the substrate serves as the drain.
Inventors
- 👤 Franco Bertotti
- 👤 Mario Foroni
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 09:16
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/83; H10D30/831; H10D84/00; H10D84/40; H10D84/401; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
191 words
A silicon wafer comprising a monocrystalline silicon substrate of one conductivity type, an epitaxially grown silicon stratum of the opposite conductivity type overlying said substrate, a buried layer of said opposite conductivity type embedded in said substrate in contact with said stratum, said buried layer having at least one enclave integral with said substrate and of said one conductivity type extending into contact with said stratum, a plurality of zones of said one conductivity type rising from said substrate to a surface of said stratum remote from said substrate, one of said zones overlying said enclave, another of said zones forming a barrier junction which separates a section of said stratum overlying said buried layer from other parts of said stratum, a first electrode on said remote surface in ohmic contact with said one of said zones, a second electrode on said remote surface in ohmic contact with said section of said stratum, and a third electrode in ohmic contact with said substrate, said enclave forming part of a channel of a field-effect transistor with a source, a gate and a drain respectively constituted by said first, second and third electrodes.
Claim 2
Dependent Claim
191 words
A silicon wafer comprising a monocrystalline silicon substrate of one conductivity type, an epitaxially grown silicon stratum of the opposite conductivity type overlying said substrate, a buried layer of said opposite conductivity type embedded in said substrate in contact with said stratum, said buried layer having at least one enclave integral with said substrate and of said one conductivity type extending into contact with said stratum, a plurality of zones of said one conductivity type rising from said substrate to a surface of said stratum remote from said substrate, one of said zones overlying said enclave, another of said zones forming a barrier junction which separates a section of said stratum overlying said buried layer from other parts of said stratum, a first electrode on said remote surface in ohmic contact with said one of said zones, a second electrode on said remote surface in ohmic contact with said section of said stratum, and a third electrode in ohmic contact with said substrate, said enclave forming part of a channel of a field-effect transistor with a source, a gate and a drain respectively constituted by said first, second and third electrodes.
Claim 3
Dependent Claim
37 words
A silicon wafer as defined in claim 1 wherein said channel comprises a plurality of enclaves spaced apart from one another in said buried layer, said one of said zones being duplicated above each of said enclaves.
Claim 4
Dependent Claim
24 words
A silicon wafer as defined in claim 1 or 2 wherein said one conductivity type is P and said opposite conductivity type is N.
Claim 5
Dependent Claim
34 words
A silicon wafer as defined in claim 3 wherein said substrate has P - conductivity, said stratum has N conductivity, said buried layer has N + conductivity and said zones have P + conductivity.
Claim 6
Dependent Claim
29 words
A silicon wafer as defined in claim 1 or 2, further comprising conductor means for short-circuiting said first and second electrodes to convert said field-effect transistor into a resistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-05-04 | 1984-11-03 | 1985-05-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-05-04 | 1988-11-03 | 1989-05-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-05-04 | 1992-11-03 | 1993-05-05 | $7700.00 | Window Closed / Lapsed |